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AD5060YRJZ-1REEL7

更新时间： 2024-01-30 07:36:17
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亚德诺 - ADI /
页数 文件大小 规格书
24页 461K
描述
Fully Accurate 14-/16-Bit VOUT nanoDAC™ SPI Interface 2.7 V to 5.5 V, in an SOT-23

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 浏览型号AD5060YRJZ-1REEL7的Datasheet PDF文件第1页浏览型号AD5060YRJZ-1REEL7的Datasheet PDF文件第2页浏览型号AD5060YRJZ-1REEL7的Datasheet PDF文件第4页浏览型号AD5060YRJZ-1REEL7的Datasheet PDF文件第5页浏览型号AD5060YRJZ-1REEL7的Datasheet PDF文件第6页浏览型号AD5060YRJZ-1REEL7的Datasheet PDF文件第7页 
AD5040/AD5060  
SPECIFICATIONS  
VDD = 5.5 V, VREF = 4.096 V @ RL = unloaded, CL = unloaded; TMIN to TMAX, unless otherwise noted.  
Table 2.  
A, B, and Y Grades1  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
STATIC PERFORMANCE  
Resolution  
16  
14  
Bits  
Bits  
LSB  
LSB  
AD5060  
AD5040  
Relative Accuracy (INL)2  
0.5  
0.5  
0.5  
0.1  
0.1  
0.5  
2
1
1.5  
2.0  
2.0  
1
−40°C to +85°C, AD5040/AD5060 A grade  
−40°C to +85°C, AD5040/AD5060 B grade  
−40°C to +125°C, AD5060 Y grade  
−40°C to +85°C, AD5040/AD5060  
−40°C to +125°C, AD5060 Y grade  
Total Unadjusted Error (TUE)2  
Differential Nonlinearity (DNL)2  
mV  
LSB  
Guaranteed monotonic,  
−40°C to +85°C, AD5040/AD5060  
0.5  
1
Guaranteed monotonic,  
−40°C to +125°C, Y grade  
Gain Error  
0.01  
0.01  
0.02  
0.03  
% of FSR  
TA = −40°C to +85°C, AD5040/AD5060  
TA = −40°C to +125°C AD5060 Y grade  
Gain Error Temperature Coefficient  
Offset Error  
1
ppm of FSR/°C  
mV  
0.02  
0.02  
1.5  
2.0  
TA = −40°C to + 85°C, AD5040/AD5060  
TA = −40°C to + 125°C, AD5060 Y grade  
Offset Error Temperature Coefficient  
Full-Scale Error  
0.5  
0.05  
μV/°C  
mV  
2.0  
2.0  
All 1s loaded to DAC register,  
AD5040 AD5060; TA = −40°C to +85°C  
All 1s loaded to DAC register,  
0.05  
TA = −40°C to +125°C, AD5060 Y grade  
OUTPUT CHARACTERISTICS3  
Output Voltage Range  
0
VREF  
V
Output Voltage Settling Time  
4
μs  
¼ scale to ¾ scale code transition to  
1 LSB, RL = 5 kΩ  
Output Noise Spectral Density  
Output Voltage Noise  
64  
6
DAC code = midscale, 1 kHz  
nV/√Hz  
μV p-p  
DAC code = midscale , 0.1 Hz to 10 Hz  
bandwidth  
Digital-to-Analog Glitch Impulse  
2
nV-s  
1 LSB change around code 57386,  
RL = 5 kΩ, CL = 200 pF  
Digital Feedthrough  
0. 003  
0. 015  
nV-s  
Ω
DAC code = full scale  
Output impedance tolerance 10%  
DC Output Impedance (Normal)  
DC Output Impedance (Power-Down)  
(Output Connected to 1 kΩ Network)4  
(Output Connected to 100 kΩ  
Network)  
1
100  
kΩ  
kΩ  
Output impedance tolerance 400 Ω  
Output impedance tolerance 20 kΩ  
Capacitive Load Stability  
Slew Rate  
1
nF  
V/μs  
Loads used RL = 5 kΩ, RL = 100 kΩ, RL = ∞  
¼ scale to ¾ scale code transition to  
1 LSB, RL = 5 kΩ, CL = 200 pF  
DAC code = full scale, output shorted to  
GND, TA = 25°C  
1. 2  
60  
Short-Circuit Current  
ma  
45  
DAC code = zero scale, output shorted to  
VDD, TA = 25°C  
DAC Power-Up Time  
4.5  
μs  
Time to exit power-down mode to normal  
mode of AD5060, 24th clock edge to 90%  
of DAC final value, output unloaded  
DC Power Supply Rejection Ratio  
−92.11  
db  
VDD 10%, DAC code = full scale  
Rev. A | Page 3 of 24  
 
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