AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
SUPERFRAME: 20.83ȝs FOR 48kHz SAMPLING RATE
SYNCH
CONTROL
FRAME
SYNCH
RESPONSE
FRAME
SYNCH
CONTROL
FRAME
DOWNSTREAM
UPSTREAM
2
2
A B DATA SLOTS
A B DATA SLOTS
Figure 3. A2B Superframe
MASTER NODE
2
I S TX
2
2
2
I S UPSTREAM DATA N
2
-
2
I S UPSTREAM DATA N
-
1
I S UPSTREAM DATA N
DATA
2
2
2
I S RX
DATA
I S DOWNSTREAM DATA M
I S DOWNSTREAM DATA M
+
1
I S DOWNSTREAM DATA M + 2
SUPERFRAME
DNSTREAM
UPSTREAM
DNSTREAM
UPSTREAM
DNSTREAM
UPSTREAM
2
2
2
2
2
2
2
A B DATA
A B DATA
A B DATA
A B DATA
A B DATA
A B DATA
A B DATA
M
-
1
N
-
1
M
N
M+1
N+1
SLAVE NODE
2
I S RX
2
2
2
I S UPSTREAM DATA N
I S UPSTREAM DATA N + 1
I S UPSTREAM DATA N + 2
DATA
2
2
2
2
I S TX
I S DOWNSTREAM DATA M
-
2
I S DOWNSTREAM DATA M
-
1
I S DOWNSTREAM DATA M
DATA
Figure 4. A2B Bus Synchronous Data Exchange
I2C INTERFACE
The I2C interface in the transceiver provides access to the inter-
nal registers. Operation is not guaranteed above the VI2C_VBUS
specification. The I2C interface has the following features:
• Slave functionality in the A2B master
• Master or slave functionality in the A2B slave
• Multimaster support in the A2B slave
• 100 kbps or 400 kbps rate operation
• 7-bit addressing
BUS_ADDR (Bit 1 = 1) to access a bus node slave transceiver
through a master configured AD2425W transceiver. See the
AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B
Transceiver Technical Reference for details.
I2S/TDM INTERFACE
The I2S/TDM serial port operates in full-duplex mode, where
both the transmitter and receiver operate simultaneously using
the same critical timing bit clock (BCLK) and synchronization
(SYNC) pins. A2B slave transceivers generate the timing signals
on the BCLK and SYNC output pins. A2B master transceivers
use the same BCLK and SYNC pins as inputs, which are driven
by the host device. The I2S/TDM port includes the following
features:
• Single-word and burst mode read and write operations
• Clock stretching
All transceivers can be accessed by a locally connected processor
using the 7-bit I2C device address (BASE_ADDR) established by
the logic levels applied to the ADR2/IO2 and ADR1/IO1 pins at
power-on reset, thus providing for up to four master devices
connecting to the same I2C bus. A slave configured transceiver
recognizes only this I2C device address. A master configured
transceiver, however, also recognizes a second I2C device
address for remote access to slave nodes over the A2B bus
(BUS_ADDR). The least significant bit (LSB) of the 7-bit device
address determines whether an I2C data exchange uses the
BASE_ADDR (Bit 1 = 0) to access the transceiver or
• Programmable clock and frame sync timing and polarity
• Numerous TDM operating modes
• 16- or 32-bit data width
• Simultaneous operation with PDM port
• Single- or dual-pin input/output (I/O)
Rev. B
|
Page 5 of 38
|
January 2020
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