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AD1955ARSRL

更新时间： 2024-01-06 08:43:24
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 903K
描述
High Performance Multibit with SACD Playback

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AD1955ARSRL 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：PLASTIC, SSOP-28
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.31商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-PDSO-G28JESD-609代码：e0
长度：10.2 mm功能数量：1
端子数量：28最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm

AD1955ARSRL 数据手册

 浏览型号AD1955ARSRL的Datasheet PDF文件第3页浏览型号AD1955ARSRL的Datasheet PDF文件第4页浏览型号AD1955ARSRL的Datasheet PDF文件第5页浏览型号AD1955ARSRL的Datasheet PDF文件第7页浏览型号AD1955ARSRL的Datasheet PDF文件第8页浏览型号AD1955ARSRL的Datasheet PDF文件第9页 
AD1955  
PIN FUNCTION DESCRIPTIONS  
Pin No.  
I/O  
Mnemonic  
Description  
1
2
DVDD  
Digital Power Supply Connected to Digital 5 V Supply  
Input  
Input  
Input  
LRCLK/EF_WCLK  
Left/Right Clock Input for Input Data in PCM Mode  
Word Clock in External Filter Mode  
3
4
BCLK/EF_BCLK  
Bit Clock Input for Input Data in PCM Mode  
Bit Clock Input in External Filter Mode  
SDATA/EF_LDATA  
MSB First, Twos Complement Serial Audio Data  
Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode  
Left Channel Data in External Filter Mode  
5
6
Input  
I/O  
EF_RDATA  
DSD_SCLK  
Not used in PCM Mode  
Right channel data in External Filter Mode  
Serial Clock Input for DSD Data. This clock should be 64 ꢀ 44.1 kHz,  
2.8224 MHz or 128 ꢀ 44.1 kHz, 5.6448 MHz in Normal Mode, 128 ꢀ  
44.1 kHz, 5.6448 MHz or 256 ꢀ 44.1 kHz, 11.2896 MHz in Phase Mode.  
7
8
9
Input  
Input  
I/O  
DSD_LDATA  
DSD_RDATA  
DSD_PHASE  
DSD Left Channel Data Input  
DSD Right Channel Data Input  
DSD Phase Reference Signal. This clock should be 64 ꢀ 44.1 kHz,  
2.8224 MHz. If not used, this pin should be connected low.  
10  
11  
12  
13  
AGND  
Analog Ground  
Output  
Output  
Output  
IOUTR+  
IOUTR–  
FILTR  
Right Channel Positive Analog Output  
Right Channel Negative Analog Output  
Voltage Reference Filter Capacitor Connection. Bypass and decouple the  
voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.  
14  
15  
16  
17  
18  
19  
20  
IREF  
Connection Point for External Bias Resistor  
Analog Power Supply Connected to Analog 5 V Supply  
Filter Capacitor Connection with Parallel 10 µF and 0.1 µF Capacitors to AGND  
Left Channel Negative Analog Output  
AVDD  
FILTB  
IOUTL–  
IOUTL+  
AGND  
ZEROR  
Output  
Output  
Output  
Left Channel Positive Analog Output  
Analog Ground  
Output  
Output  
Input  
Right Channel Zero Flag Output. This pin goes high when the right channel  
has no signal input or the DSD mute pattern is detected.  
21  
22  
23  
ZEROL  
MUTE  
PD/RST  
Left Channel Zero Flag Output. This pin goes high when the left channel has  
no signal input or the DSD mute pattern is detected.  
Mute. Assert high to mute both stereo analog outputs. Deassert low for nor-  
mal operation.  
Input  
Power Down/Reset. The AD1955 is placed in a reset state and the digital  
circuitry is powered down when this pin is held low. The AD1955 is reset on  
the rising edge of this signal. The serial control port registers are reset to the  
default values. Connect high for normal operation.  
24  
Input  
CDATA  
Serial Control Input, MSB First, Containing 16 Bits of Unsigned Data. Used  
for specifying control information and channel-specific attenuation.  
25  
26  
Input  
Input  
CLATCH  
Latch Input for Control Data  
CCLK  
Clock Input for Control Data. Control input data must be valid on the rising  
edge of CCLK. CCLK may be continuous or gated.  
27  
28  
Input  
MCLK  
DGND  
Master Clock Input. Connect to an external clock source.  
Digital Ground  
–6–  
REV. 0  
1...3456789...24

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