Datasheet > AD1941_15

AD1941_15

更新时间： 2022-02-26 13:17:30

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
36页	421K
描述
SigmaDSP Multichannel 28-Bit Audio Processor

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AD1941_15 数据手册

AD1940/AD1941

SPECIFICATIONS

Test conditions, unless otherwise noted.

Table 1.

Parameter

Conditions

Supply Voltage (VDD)

PLL Voltage (PLL_VDD)

Output Voltage (ODVDD)

INVDD Voltage

2.5 V

5.0 V

Ambient Temperature

Master Clock Input

Load Capacitance

Load Current

Input Voltage, HI

Input Voltage, LO

25°C

3.072 MHz, 64 × f_smode

50 pF

±± mA

2.4 V

0.8 V

DIGITAL I/O

VDD = 2.25 V to 2.75 V. Specifications measured across −40°C to 125°C (case).

Table 2.

Parameter

Comments

Min

Max

Unit

μA

Input Voltage, HI (V_IH)

Input Voltage, LO (V_IL)

Input Leakage (I_IH)

Input Leakage (I_IL)

High Level Output Voltage (V_OH

Low Level Output Voltage (V_OL

Input Capacitance

2.±

0.8

±0

)

ODVDD = 4.5 V, I_OH= ± mA

ODVDD = 3.0 V, I_OH= ± mA

ODVDD = 4.5 V, I_OL= ± mA^±

ODVDD = 3.0 V, I_OL= ± mA^±

3.9

2.6

)

0.4

0.3

^±SDA is measured with a 3 mA sink current.

POWER

Table 3.

Parameter

Min

2.25

Typ

Max¹

Unit

SUPPLIES

Voltage

Digital Current

PLL Current

Digital Current, Reset

PLL Current, Reset

DISSIPATION

Operation, All Supplies

Reset, All Supplies

2.5

3.5

4.5³

2.75

±55²

±3³

8.5

238.8

±0.8

^±Maximum specifications are measured across −40°C to ±25°C (case) and across VDD = 2.25 V to 2.75 V.

²Measurement running a typical large program that writes to all ±6 outputs with 0 dB digital sine waves applied to all eight inputs. The end user’s program may differ.

³The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.

Rev. B | Page 3 of 36

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