Datasheet > 暂无类别数据> AD1938WBSTZRL

AD1938WBSTZRL

更新时间： 2024-01-11 09:40:29

品牌	Logo	应用领域
亚德诺 - ADI		解码器编解码器
页数	文件大小	规格书
30页	382K
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数据手册

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AD1938WBSTZRL 数据手册

Preliminary Technical Data

AD1935/AD1936/AD1937/AD1938/AD1939

Parameter

f_CCLK

t_CDS

Comments

Min

Max

Unit

MHz

CCLK Frequency

CDATA Setup

CDATA Hold

To CCLK Rising

TBD

t_CDH

From CCLK Rising

To CCLK Rising

t_CLS

CLATCH

Setup

Hold

High

t_CLH

From CCLK Falling

t_CLH

t_COE

COUT Enable

COUT Delay

From CCLK Falling

TBD

t_COD

t_COH

COUT Hold

TBD

t_COTS

f_SCL

COUT Three-State

TBD

400

SCL Clock

Frequency

kHz

t_SCLH

t_SCLL

t_SCS

SCL High

SCL Low

0.6

1.3

0.6

µS

Setup Time

Relevant for Repeated Start

Condition

t_SCH

Hold Time

After this period the 1st clock is

generated

0.6

µS

I²C PORT

t_DS

Data Setup Time

SCL Rise Time

SCL Fall Time

SDA Rise Time

SDA Fall Time

Setup Time

100

µS

Start Condition

t_SCR

t_SCF

t_SDR

t_SDF

t_SCS

t_DBH

t_DBL

f_DB

300

Stop Condition

Slave Mode

0.6

DBCLK High

TBD

DBCLK Low

DBCLK Frequency

DLRCLK Setup

DLRCLK Hold

DLRCLK Skew

DSDATA Setup

DSDATA Hold

ABCLK High

t_DLS

t_DLH

t_DLS

t_DDS

t_DDH

t_ABH

t_ABL

f_DB

To DBCLK Rising

DAC SERIAL PORT

From DBCLK Rising

From DBCLK Falling

To DBCLK Rising

Master Mode

TBD

From DBCLK Rising

ABCLK Low

Slave Mode

ABCLK Frequency

ALRCLK Setup

ALRCLK Hold

ALRCLK Skew

ASDATA Delay

AAUXDATA Setup

AAUXDATA Hold

DAUXDATA Delay

AUXBCLK High

AUXBCLK Low

ADC SERIAL PORT

t_ALS

t_ALH

t_ALS

t_ABDD

t_AXDS

t_AXDH

t_DXDD

t_XBH

t_XBL

f_XB

To ABCLK Rising

From ABCLK Rising

From ABCLK Falling

To AUXBCLK Rising

From AUXBCLK Rising

From AUXBCLK Falling

Master Mode

TBD

AUXILIARY INTERFACE

AUXBCLK

Frequency

t_DLS

t_DLH

AUXLRCLK Setup

AUXLRCLK Hold

To AUXBCLK Rising

TBD

From AUXBCLK Rising

Table 8

Rev. PrI | Page 5 of 30

1 2 3 456 7 8...30

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