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AD1938WBSTZRL

更新时间： 2024-01-22 19:26:22

品牌	Logo	应用领域
亚德诺 - ADI		解码器编解码器
页数	文件大小	规格书
30页	382K
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AD1938WBSTZRL 数据手册

Preliminary Technical Data

AD1935/AD1936/AD1937/AD1938/AD1939

Temperature Range

Parameter

Min

Typ

Max

Unit

Specifications Guaranteed

°C Case

°C Ambient

°C Case

°C

–40

–65

+105

+125

+150

Functionality Guaranteed

Storage

Table 6

Digital Filters

Mode

Parameter

Factor

Min

Typ

0.015

Max

Unit

kHz

Pass Band

0.4375 f_S

Pass-Band Ripple

Transition Band

Stop Band

ADC

DECIMATION

FILTER

All Modes,

Typ @ 48 kHz

0.5 f_S

kHz

0.5625 f_S

Stop-Band Attenuation

Group Delay

22.9844/ f_S

0.4535 f_S

479

µs

Pass Band

kHz

Pass-Band Ripple

Transition Band

Stop Band

0.01

48 kHz Mode,

Typ @ 48 kHz

0.5 f_S

kHz

0.5465 f_S

Stop-Band Attenuation

Group Delay

25/ f_S

521

µs

Pass Band

0.3646 f_S

kHz

Pass-Band Ripple

Transition Band

Stop Band

0.05

DAC

INTERPOLATION

FILTER

96 kHz Mode,

Typ @ 96 kHz

0.5 f_S

kHz

0.6354 f_S

Stop-Band Attenuation

Group Delay

11/ f_S

115

µs

Pass Band

0.3646 f_S

kHz

Pass-Band Ripple

Transition Band

Stop Band

0.1

192 kHz Mode,

Typ @ 192 kHz

0.5 f_S

kHz

0.6354 f_S

122

Stop-Band Attenuation

Group Delay

8/ f_S

µs

Table 7

Timing Specifications

Parameter

Comments

Min

Max

Unit

t_MH

MCLK High

MCLK Low

MCLK Period

PLL Mode

6.9

t_ML

t_MCLK

f_MCLK

t_MH

PLL Mode, 256 f_Sreference

Direct 512 f_SMode

146

MCLK Frequency

MCLK High

13.8

MHz

MASTER CLOCK AND RESET

t_ML

MCLK Low

Direct 512 f_SMode

t_MCLK

f_MCLK

t_PDR

t_PDRR

t_CCH

t_CCL

MCLK Period

MCLK Frequency

Direct 512 f_SMode

27.6

MHz

PD/RST

TBD

Low

Reset to Active Output

t_MCLK

Recovery

SPI PORT

CCLK High

CCLK Low

CCLK Period

t_CCP

Rev. PrI | Page 4 of 30

1 2 345 6 7...30

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