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AD1890JN

更新时间： 2024-01-23 12:54:53
品牌 Logo 应用领域
亚德诺 - ADI 转换器商用集成电路光电二极管
页数 文件大小 规格书
20页 418K
描述
SamplePort Stereo Asynchronous Sample Rate Converters

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AD1890JN 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：PLASTIC, LCC-28针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.57
Is Samacsys：N商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-PQCC-J28JESD-609代码：e3
长度：11.5062 mm湿度敏感等级：3
端子数量：28最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Other Consumer ICs最大压摆率：40 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：11.5062 mmBase Number Matches：1

AD1890JN 数据手册

 浏览型号AD1890JN的Datasheet PDF文件第1页浏览型号AD1890JN的Datasheet PDF文件第2页浏览型号AD1890JN的Datasheet PDF文件第3页浏览型号AD1890JN的Datasheet PDF文件第5页浏览型号AD1890JN的Datasheet PDF文件第6页浏览型号AD1890JN的Datasheet PDF文件第7页 
AD1890/AD1891  
(continued from Page 1)  
GPDLYS (AD1890)  
N/C (AD1891)  
1
2
28 SETSLW  
27 GND  
SERIAL IN  
P RO D UCT O VERVIEW (Continued)  
MCLK  
DATA_I  
BCLK_I  
WCLK_I  
LR_I  
automatically limited to avoid alias distortion on the output sig-  
nal. T he AD1890/AD1891 dynamically alter the low-pass filter  
cutoff frequency smoothly and slowly, so that real-time varia-  
tions in the sample rate ratio are possible without degradation of  
the audio quality.  
3
BCLK_O  
WCLK_O  
LR_O  
26  
25  
24  
23  
22  
SERIAL OUT  
4
5
ACCUM  
6
DATA_O  
T he AD1890/AD1891 have a pin selectable slow- or fast-settling  
mode. T his mode determines how quickly the ASRCs adapt to a  
change in either the input sample clock frequency (FSIN) or the  
output sample clock frequency (FSOUT ). In the slow-settling  
mode, the control loop which computes the ratio between FSIN  
and FSOUT settles in approximately 800 ms and begins to reject  
jitter above 3 Hz. T he slow-settling mode offers the best signal  
quality and the greatest jitter rejection. In the fast-settling mode,  
the control loop settles in approximately 200 ms and begins to  
reject jitter above 12 Hz. T he fast-settling mode allows rapid,  
real time sample rate changes to be tracked without error, at the  
expense of some narrow-band noise modulation products on the  
output signal.  
7
V
V
DD  
DD  
MULT  
8
21 GND  
GND  
N/C  
9
20 N/C  
10  
11  
12  
13  
14  
19 BKPOL_O  
18 TRGLR_O  
BKPOL_I  
TRGLR_I  
MSBDLY_I  
RESET  
COEF ROM  
FIFO  
17  
16  
15  
MSBDLY_O  
MUTE_O  
MUTE_I  
CLOCK  
TRACKING  
GND  
AD1890/AD1891  
N/C = NO CONNECT  
T he AD1890 also has a pin selectable, short or long group delay  
mode. T his pin determines the depth of the First-In, First-Out  
(FIFO) memory which buffers the input data samples before  
they are processed by the FIR convolver. In the short mode, the  
group delay is approximately 700 µs. T he ASRC is more sensi-  
tive to sample rate changes in this mode (i.e., the pointers which  
manage the FIFO are more likely to cross and become momen-  
tarily invalid during a sample rate step change), but the group  
delay is minimized. In the long mode, the group delay is ap-  
proximately 3 ms. T he ASRC is tolerant of large dynamic  
sample rate changes in this mode, and it should be used when  
the device is required to track fast sample rate changes, such as  
in varispeed applications. T he AD1891 features the short group  
delay mode only. In either device, if the read and write pointers  
that manage the FIFO cross (indicating underflow or overflow),  
the ASRC asserts the mute output (MUT E_O) pin HI for 128  
output clock cycles. If MUT E_O is connected to the mute input  
(MUT E_I) pin, as it normally should be, the serial output will  
be muted (i.e., all bits zero) during this transient event.  
AD1890/AD1891 DIP Pinout  
4
3
2
1
28  
27  
26  
SERIAL IN  
SERIAL OUT  
5
25  
24  
23  
22  
WCLK_I  
WCLK_O  
LR_O  
6
LR_I  
ACCUM  
MULT  
7
V
DATA_O  
DD  
8
GND  
V
DD  
9
21 GND  
20  
19 BKPOL_O  
N/C  
COEF ROM  
FIFO  
10  
N/C  
BKPOL_I  
CLOCK  
TRACKING  
11  
TRGLR_I  
T he AD1890/AD1891 are fabricated in a 0.8 µm single poly,  
double metal CMOS process and are packaged in a 0.6" wide  
28-pin plastic DIP and a 28-pin PLCC. T he AD1890/AD1891  
operate from a +5 V power supply over the temperature range of  
0°C to +70°C.  
AD1890/AD1891  
12  
13  
14  
15  
16  
17  
18  
N/C = NO CONNECT  
AD1890/AD1891 PLCC Pinout  
REV. 0  
–4–  
1234567...20

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