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AD1892 PDF预览

AD1892

更新时间: 2024-01-04 10:11:43
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
24页 234K
描述
Integrated Digital Receiver/Rate Converter

AD1892 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.69商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:17.9 mm湿度敏感等级:3
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Other Consumer ICs
最大压摆率:60 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

AD1892 数据手册

 浏览型号AD1892的Datasheet PDF文件第2页浏览型号AD1892的Datasheet PDF文件第3页浏览型号AD1892的Datasheet PDF文件第4页浏览型号AD1892的Datasheet PDF文件第5页浏览型号AD1892的Datasheet PDF文件第6页浏览型号AD1892的Datasheet PDF文件第7页 
Integrated Digital  
a
Receiver/Rate Converter  
AD1892  
FEATURES  
PRODUCT OVERVIEW  
Complete EIAJ CP-340 (CP-1201), IEC-958, AES/EBU,  
S/PDIF Compatible Digital Audio Receiver and  
Asynchronous Sample Rate Converter  
Status Pins and Microprocessor Interfaces for  
Stand-Alone and Microcontroller-Oriented Operation  
Integrated Channel Status Buffer and Q-Channel  
Subcode Buffer (Supports EIAJ CP-2401)  
20-Bit SamplePort® Architecture Provides Superb Jitter  
Rejection on Input Port  
Sample Rate Conversion from 8 kHz to 48 kHz with  
1:5 Upsampling Range  
1:0.85 Downsampling Range  
120 dB Dynamic Range  
–113 dB THD+N @ 1 kHz  
CRC Calculation on Q-Channel Subcode (Consumer  
Mode Only) and on Channel Status (Pro Mode Only)  
Four-Wire SPI™ Compatible Serial Control Port  
Mute Input Pin  
Power-Down Mode  
Single +5 V Supply  
Flexible Three-Wire Serial Data Port with Left-Justified,  
Right-Justified and I2S-Compatible Modes  
28-Lead SOIC Package  
The AD1892 combines a CP-1201, CP-340, IEC-958, AES/  
EBU, S/PDIF compatible Digital Audio Receiver (DAR) with  
an asynchronous sample rate converter, allowing the user to  
specify the output sample rate of the received digital audio infor-  
mation. The DAR block features support for both Q-channel  
subcode information (to support CD, CD-R, MD and DAT  
digital audio formats) as well as Channel Status information. A  
microcontroller interface, with an SPI compatible serial port,  
allows full access to the 80-bit Q-Channel subcode buffer and to  
the 32-bit Channel Status buffer, as well as to the control and  
status registers. Additionally, key status information from the  
incoming subframes and the Channel Status buffer is reported  
on status output pins on the AD1892, so the AD1892 may be  
used in systems that do not include a microcontroller or  
microprocessor.  
The asynchronous sample rate converter block is based on  
market leading AD1890 family SamplePort rate conversion tech-  
nology. The AD1892 offers a 1:5 upsampling range, and will  
downsample from 48 kHz to 44.1 kHz. Input audio word widths  
up to 20 bits are supported, and output audio word widths of 16  
or 20 are supported, with 120 dB of dynamic range and –113 dB  
THD+N. The rate converter inherently rejects jitter on the  
recovered clocks from the incoming biphase-mark encoded  
stream. Indeed, sample rate conversion is highly synergistic  
with digital audio reception, allowing the use of a fully digital  
phase locked loop clock recovery scheme with highly robust  
clock recovery and jitter rejection.  
APPLICATIONS  
DVD, DAT, MD, DCC and CD-R Recorders and Players  
Computer Multimedia Products  
DAB Receivers, Automotive Digital Audio Networks  
(continued on Page 4)  
FUNCTIONAL BLOCK DIAGRAM  
512 x F  
SOUT  
POWER-DOWN/RESET  
MUTE  
BCLK  
LRCLK  
SDATA  
3
CLOCK  
GENERATOR  
ASYNCH SAMPLE  
RATE CONVERTER  
OUTPUT SERIAL  
INTERFACE  
DATA  
BYPASS  
SYNC  
2
BIPHASE-MARK  
INPUT  
BIPHASE-MARK  
RECEIVER  
COMPARATOR  
CONTROL  
CA  
CB  
CC  
CD  
CRC  
CHECK  
CRC  
Q-CHANNEL  
CHANNEL STATUS  
BUFFER  
CHECK SUBCODE BUFFER  
AD1892  
CE  
MICROCONTROLLER  
INTERFACE  
CON/PRO  
CSCLK  
4
2
U/C BIT  
INTERRUPT  
SFCLK  
CLOCK, LATCH,  
DATA IN,  
DATA OUT  
DIGITAL  
SUPPLY  
NO  
SIGNAL  
ERROR  
QDFS  
SamplePort is a registered trademark of Analog Devices, Inc.  
SPI is a trademark of Motorola, Inc.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1998  

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