AD1861

更新时间： 2024-02-14 20:41:32

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器 PC
页数	文件大小	规格书
12页	199K
描述
16-Bit/18-Bit, 16 X Fs PCM Audio DACs

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AD1861 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.8
Is Samacsys：	N	最大模拟输出电压：	3.12 V
最小模拟输出电压：	-2.88 V	转换器类型：	D/A CONVERTER
输入位码：	2'S COMPLEMENT BINARY	输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
长度：	10.3 mm	湿度敏感等级：	1
标称负供电电压：	-5 V	位数：	18
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	认证状态：	COMMERCIAL
座面最大高度：	2.65 mm	标称安定时间 (tstl)：	1.5 µs
标称供电电压：	5 V	表面贴装：	YES
技术：	BICMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	7.5 mm
Base Number Matches：	1

AD1861 数据手册

AD1851/AD1861

TO TAL H ARMO NIC D ISTO RTIO N

T otal harmonic distortion plus noise (T HD+N) is defined as

the ratio of the square root of the sum of the squares of the val-

ues of the first 19 harmonics and noise to the value of the funda-

mental input frequency. It is usually expressed in percent (%).

DAC

REFERENCE

OUT

AUDIO

OUTPUT

T HD+N is a measure of the magnitude and distribution of lin-

earity error, differential linearity error, quantization error and

noise. T he distribution of these errors may be different, depend-

ing on the amplitude of the output signal. T herefore, to be most

useful, T HD+N should be specified for both large (0 dB) and

small signal amplitudes (–20 dB and –60 dB).

INPUT LATCH

SERIAL-TO-PARALLEL

CONVERSION

CLOCK

DATA

T he T HD+N figure of an audio DAC represents the amount of

undesirable signal produced during reconstruction and playback

of an audio waveform. T his specification, therefore, provides a

direct method to classify and choose an audio DAC for a

desired level of performance.

Figure 1. AD1851/AD1861 Functional Block Diagram

FUNCTIO NAL D ESCRIP TIO N

T he AD1851/AD1861 is a complete monolithic PCM audio

DAC. No additional external components are required for op-

eration. As shown in Figure 1 above, each chip contains a volt-

age reference, an output amplifier, a DAC, an input latch and a

parallel input register.

SETTLING TIME

Settling time is the time required for the output of the DAC to

reach and remain within a specified error band about its final

value, measured from the digital input transition. It is a primary

measure of dynamic performance.

T he voltage reference consists of a bandgap circuit and buffer

amplifier. T his combination of elements produces a reference

voltage that is unaffected by changes in temperature and age.

T he DAC output voltage, which is derived from the reference

voltage, is also unaffected by these environmental changes.

MID SCALE ERRO R

Midscale error, or bipolar zero error, is the deviation of the ac-

tual analog output from the ideal output (0 V) when the 2s

complement input code representing half scale is loaded in the

input register.

T he output amplifier uses both MOS and bipolar devices to

produce low offset, high slew rate and optimum settling time.

When combined with the on-chip feedback resistor, the output

op amp converts the output current of the AD1851/AD1861 to

a voltage output.

D -RANGE D ISTO RTIO N

D-range distortion is equal to the value of the total harmonic

distortion + noise (T HD+N) plus 60 dB when a signal level of

–60 dB below full scale is reproduced. D-range is tested with a

1 kHz input sine wave. T his is measured with a standard A-

weight filter as specified by EIAJ Standard CP-307.

T he DAC uses a combination of segmented decoder and R-2R

architecture to achieve consistent linearity and differential lin-

earity. T he resistors which form the ladder structure are fabri-

cated with silicon chromium thin film. Laser-trimming of these

resistors further reduces linearity error, resulting in low output

distortion.

SIGNAL-TO -NO ISE RATIO

T he signal-to-noise ratio (SNR) is defined as the ratio of the

amplitude of the output when a full-scale output is present to

the amplitude of the output with no signal present. T his is mea-

sured with a standard A-weight filter as specified by EIAJ

Standard CP-307.

T he input register and serial-to-parallel converter are fabricated

with CMOS logic gates. T hese gates allow the achievement of

fast switching speeds and low power consumption. T his contrib-

utes to the overall low power dissipation of the AD1851/

AD1861.

REV. A

–5–

1 2 3 456 7 8...12

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与AD1861相关器件

型号	品牌	描述	获取价格	数据表
AD1861N	ADI	16-Bit/18-Bit, 16 X Fs PCM Audio DACs	获取价格
AD1861N	ROCHESTER	SERIAL INPUT LOADING, 1.5us SETTLING TIME, 18-BIT DAC, PDIP16, PLASTIC, DIP-16	获取价格
AD1861N-J	ADI	16-Bit/18-Bit, 16 X Fs PCM Audio DACs	获取价格
AD1861NZ-J	ADI	暂无描述	获取价格
AD1861R	ADI	16-Bit/18-Bit, 16 X Fs PCM Audio DACs	获取价格
AD1861R-J	ADI	16-Bit/18-Bit, 16 X Fs PCM Audio DACs	获取价格

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