Datasheet > AD1858_15

AD1858_15

更新时间： 2022-02-26 13:17:30

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	266K
描述
Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs

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AD1858_15 数据手册

AD1857/AD1858–SPECIFICATIONS

TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED

Supply Voltages (AV_DD, DV_DD

Ambient T emperature

)

+5.0 V

25°C

Input Clock (F_MCLK

Input Signal

)

11.2896 MHz (256 × F_SMode)

1.0013 kHz

–0.5 dB Full Scale

44.1 kHz

20 Hz to 20 kHz

18 Bits

Input Sample Rate

Measurement Bandwidth

AD1857 Input Data Wordwidth

AD1858 Input Data Wordwidth

Load Capacitance

16 Bits

100 pF

Load Impedance

47 kΩ

Input Voltage HI (V_IH

)

2.4 V

Input Voltage LO (V_IL)

0.8 V

I²S-Justified Mode (Ref. Figure 7) for AD1857, Right-Justified Mode (Ref. Figure 8) for AD1858.

Performance of the right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).

Values in bold typeface are tested, all others are guaranteed, not tested.

ANALO G P ERFO RMANCE

Min

Typ

Max

Units

AD1857 Resolution

AD1858 Resolution

Bits

Dynamic Range (20 Hz to 20 kHz, –60 dB Input)

No A-Weight Filter

With A-Weight Filter

–90

0.003

T otal Harmonic Distortion + Noise

–85

0.006

Analog Outputs

Single-Ended Output Range (± Full Scale)

Output Impedance at Each Output Pin

Output Capacitance at Each Output Pin

Out-of-Band Energy (0.5 × F_Sto 100 kHz)

CMOUT

2.8

3.0

<200

3.2

V p-p

Ω

–72.5

2.4

2.1

2.25

DC Accuracy

Gain Error

Interchannel Gain Mismatch

Gain Drift

Interchannel Crosstalk (EIAJ method)

Interchannel Phase Deviation

Mute Attenuation

±3.0

0.01

150

–120

±0.1

–100

؎7.5

؎0.2

300

ppm/°C

Degrees

–100

–90

De-emphasis Gain Error

±0.1

D IGITAL I/O

Min

Max

Units

Input Voltage HI (V_IH

)

2.4

Input Voltage LO (V_IL)

0.8

Input Leakage (I_IH@ V_IH= 2.4 V)

Input Leakage (I_IL@ V_IL= 0.8 V)

Input Capacitance

µA

REV. 0

–2–

123 4 5 6 7...16

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