AD1674KR

更新时间： 2024-02-15 04:02:26

品牌	Logo	应用领域
亚德诺 - ADI		转换器光电二极管信息通信管理
页数	文件大小	规格书
12页	257K
描述
12-Bit 100 kSPS A/D Converter

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD1674KR 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP28,.4	针数：	28
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.19
Is Samacsys：	N	最大模拟输入电压：	10 V
最小模拟输入电压：	-10 V	最长转换时间：	10 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	17.9 mm
最大线性误差 (EL)：	0.0122%	湿度敏感等级：	3
标称负供电电压：	-15 V	模拟输入通道数量：	1
位数：	12	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		输出位码：	BINARY
输出格式：	PARALLEL, WORD	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP28,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	5,+-12/+-15 V
认证状态：	Not Qualified	采样速率：	0.111 MHz
采样并保持/跟踪并保持：	SAMPLE	座面最大高度：	2.65 mm
子类别：	Analog to Digital Converters	最大压摆率：	18 mA
标称供电电压：	15 V	表面贴装：	YES
技术：	BICMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	7.5 mm
Base Number Matches：	1

AD1674KR 数据手册

AD1674

GRO UND ING

P ACKAGE INFO RMATIO N

If a single AD1674 is used with separate analog and digital

ground planes, connect the analog ground plane to AGND and

the digital ground plane to DGND keeping lead lengths as short

as possible. T hen connect AGND and DGND together at the

AD1674. If multiple AD1674s are used or the AD1674 shares

analog supplies with other components, connect the analog and

digital returns together once at the power supplies rather than at

each chip. T his prevents large ground loops which inductively

couple noise and allow digital currents to flow through the ana-

log system.

D imensions shown in inches and (mm).

28-P in Ceram ic D IP P ackage (D -28)

0.505 (12.83)

0.59 ±0.01

(14.98 ±0.254)

PIN 1

GENERAL MICRO P RO CESSO R INTERFACE

CO NSID ERATIO NS

0.050 ±0.010

(1.27 ±0.254)

0.095

(2.41)

1.42 (36.07)

1.40 (35.56)

A typical A/D converter interface routine involves several opera-

tions. First, a write to the ADC address initiates a conversion.

T he processor must then wait for the conversion cycle to com-

plete, since most ADCs take longer than one instruction cycle to

complete a conversion. Valid data can, of course, only be read

after the conversion is complete. T he AD1674 provides an out-

put signal (ST S) which indicates when a conversion is in

progress. T his signal can be polled by the processor by reading

it through an external three-state buffer (or other input port).

T he ST S signal can also be used to generate an interrupt upon

completion of a conversion, if the system timing requirements

are critical (bear in mind that the maximum conversion time of

the AD1674 is only 10 microseconds) and the processor has

other tasks to perform during the ADC conversion cycle. An-

other possible time-out method is to assume that the ADC will

take 10 microseconds to convert, and insert a sufficient number

of “no-op” instructions to ensure that 10 microseconds of pro-

cessor time is consumed.

0.145 ±0.02

(3.68 ±0.51)

0.125

(3.17)

MIN

0.010 ±0.002

(0.254 ±0.05)

0.085

(2.16)

0.6 (15.24)

SEATING

PLANE

0.047 ±0.007

(1.19 ±0.178)

0.1 (2.54)

0.017 ±0.003

(0.43 ±0.076)

28-Lead P lastic D IP P ackage (N-28)

0.550 (13.97)

0.530 (13.462)

PIN 1

0.606 (15.39)

0.594 (15.09)

1.450 (38.83)

1.440 (35.576)

0.160 (4.06)

0.140 (3.56)

0.200

(5.080)

MAX

0.012 (0.305)

0.008 (0.203)

0°

0.175 (4.45)

0.105 (2.67)

0.065 (1.65)

0.045 (1.14)

0.020 (0.508)

0.015 (0.381)

0.120 (3.05)

SEATING

PLANE

0.095 (2.41)

Once it is established that the conversion is finished, the data

can be read. In the case of an ADC of 8-bit resolution (or less),

a single data read operation is sufficient. In the case of convert-

ers with more data bits than are available on the bus, a choice of

data formats is required, and multiple read operations are

needed. T he AD1674 includes internal logic to permit direct in-

terface to 8-bit or 16-bit data buses, selected by the 12/8 input.

In 16-bit bus applications (12/8 HIGH) the data lines (DB11

through DB0) may be connected to either the 12 most signifi-

cant or 12 least significant hits of the data bus. T he remaining

four bits should be masked in software. T he interface to an 8-bit

data bus (12/8 LOW) contains the 8 MSBs (DB11 through

DB4). T he odd address (A₀HIGH) contains the 4 LSBs (DB3

through DB0) in the upper half of the byte, followed by four

trailing zeroes, thus eliminating bit masking instructions.

28-Lead Wide-Body SO P ackage (R-28)

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

PIN 1

0.3937 (10.00)

0.1043 (2.65)

0.7125 (18.10)

0.0926 (2.35)

0.6969 (17.70)

0.0291 (0.74)

x 45°

0.0098 (0.25)

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500 (1.27)

BSC

0.0125 (0.32)

0.0091 (0.23)

AD1674 Data Form at for 8-Bit Bus

–12–

REV. C

1...9 10 1112

下载PDF

与AD1674KR相关器件

型号	品牌	描述	获取价格	数据表
AD1674KRZ-REEL	ADI	12-Bit, 100 kSPS, Complete ADC	获取价格
AD1674T	ADI	12-Bit 100 kSPS A/D Converter	获取价格
AD1674TD	ADI	12-Bit 100 kSPS A/D Converter	获取价格
AD1674TD/883B	ETC	Analog-to-Digital Converter， 12-Bit	获取价格
AD1678JN	ADI	IC 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP28, PLASTIC, DIP-28, Analog to Digit	获取价格
AD1678KN	ADI	IC 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP28, PLASTIC, DIP-28, Analog to Digit	获取价格

与AD1674KR相关文章

VIPER22A的资料手册解读、引脚参数说明、代换型号推荐
2024-05-14

6
ADS1256的资料手册解读、采集电压范围、读数变化原因分析及实际测量遇到的问题
2024-05-14

8
MAX6675资料手册参数详解、引脚配置说明
2024-05-13

13
LM258引脚图及功能介绍、主要参数分析
2024-05-13

11

产品中心

服务支持

精选活动

关于我们

帮助中心

AD1674KR

AD1674KR 技术参数

AD1674KR 数据手册

与AD1674KR相关器件

与AD1674KR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD1674KR

AD1674KR 技术参数

AD1674KR 数据手册

与AD1674KR相关器件

与AD1674KR相关文章

您还可以找

您在本页遇到什么问题？