32-Channel, 3 V/5 V, Single-Supply,
14-Bit, Voltage Output DAC
AD5382
FEATURES
INTEGRATED FUNCTIONS
Guaranteed monotonic
Channel monitor
INL error: 4 LSB max
Simultaneous output update via LDAC
Clear function to user programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces:
Parallel
APPLICATIONS
Serial (SPI®/QSPI™/MICROWIRE™/DSP compatible,
featuring data readback)
I2C® compatible
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVDD (×3)
DGND (×3)
AVDD (×4)
AGND (×4)
DAC GND (×4)
REFGND
REFOUT/REFIN SIGNAL GND (×4)
PD
SER/PAR
AD5382
1.25V/2.5V
REFERENCE
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
14
14
14
14
14
14
14
14
14
14
DAC
REG 0
INPUT
REG 0
DAC 0
VOUT0
DB13/(DIN/SDA)
DB12/(SCLK/SCL)
DB11/(SPI/I2C)
DB10
14
14
m REG 0
c REG 0
FIFO
+
STATE
MACHINE
+
R
R
R
R
R
R
R
R
INTERFACE
CONTROL
LOGIC
14
14
14
14
INPUT
REG 1
DAC
DAC 1
DB0
CONTROL
LOGIC
REG 1
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
14
14
A4
A0
m REG 1
c REG 1
REG 0
REG 1
RESET
BUSY
CLR
14
INPUT
REG 6
DAC
DAC 6
REG 6
POWER-ON
RESET
14
14
m REG 6
c REG 6
14
INPUT
REG 7
DAC
V
0………V
31
OUT
OUT
DAC 7
REG 7
VOUT7
VOUT8
14
14
MON_IN1
MON_IN2
MON_IN3
MON_IN4
m REG 7
c REG 7
36-TO-1
MUX
VOUT31
×4
MON_OUT
LDAC
Figure 1.
Rev. 0
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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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