Transmit monitor TXMON and TXFLAG
Transmission Clock TCLK
TXMON is used to monitor the current delivered to There are 16 independent Transmit clocks
the LED or Laser. TXMON is a current source that TCLK(16:1) on the ACS4110. For the purpose of
proportionally mirrors the current flow through the this specification, these signals will be referred to
LED or Laser. By placing an appropriate external collectively as TCLK. The ACS4110 gives a choice
resistor RTXMON between TXMON and GND, the between internally and externally generated transmit
voltage developed (referenced to GND), will be clocks. When the CKC pin is held Low, the set of
proportional to the transmit current. During the Laser TCLK clocks are configured as outputs producing a
setup procedure TXMON should be monitored to clock at the frequency defined by DR(3:1).
ensure that the Laser manufacturer's maximum
When the CKC pin is held High, the set of TCLK
current specification is not exceeded.
clocks are configured as inputs, and will accept an
The transmit current monitor is a current source externally produced transmission clock with a
flowing from VDD out of pin TXMON. This current is tolerance of up to 250ppm with respect to the
representative of the Laser/LED drive current.
transmission rate determined by DR(3:1).
ITXMON = IBIAS/50 + IMOD/100
The data appearing on TPOS/TNEG is valid on the
rising or falling edge of the TCLK clock dependent
on the setting of TRSEL (see Figure 22. Timing
diagrams). This is the case for both internally and
externally generated transmission clocks.
IBIAS is the Low level bias current.
IMOD is the peak Modulation level bias current. The
average modulation current is half this value.
Average drive current, IAVG = (IBIAS + IMOD) /2
Therefore ITXMON = IAVG/50
Receive Clock RCLK
There are 16 independent Receive clocks
TXMON may also be employed during normal RCLK(16:1) on the ACS4110. For the purpose of
operation to continuously check the Laser current. this specification, these signals will be referred to
The voltage developed across RTXMON is compared collectively as RCLK.
within an internally generated reference voltage of
The data appearing on RPOS/RNEG is valid on the
1.25V. In the event that the reference voltage is
rising or falling edge of the RCLK clock dependent
exceeded, the TXFLAG is set High, otherwise it is
on the setting of RESEL (see Figure 22. Timing
set Low. In this way, the value of resistor on TXMON
diagrams). To ensure that the average receive
can be chosen to activate TXFLAG at any desired
frequency is the same as the transmitted frequency,
transmit current
RCLK is generated from a Phase-Lock Loop (PLL)
e.g. If RTXMON = 1KΩ, then TXFLAG will be set if IAVG system (except where master mode has been
exceeds 62.5mA.
selected). The PLL makes periodic corrections to
the output RCLK clock by subtracting or adding a
single crystal clock bit-period, so that the average
frequency of the RCLK clock tracks the average
frequency of the transmit clock of the far-end modem
(or system master clock). This decompression/de-
jittering function is covered in more detail in section
headed, Jitter Characteristics.
If desired, TXFLAG activation can be delayed by
adding a damping capacitor between TXMON and
GND.
Receive Monitor RXMON and RXFLAG
The ACS9020 incorporates a power meter which
generatesacurrentsourcewhichisproportionaltothe
received optical current.
The recovery and de-jittering functions comply to jitter
tolerance and jitter transfer specifications of the
selected data rates. The algorithm that determines
the transfer function and response of the PLLs is
modified (shaped) according to the selected data rate.
There is an internal resistor of value of 50KΩ +/- 20 %
connected between RXMON and GND which
converts the current into a voltage.
RXMON is compared with 1.25V. If RXMON exceeds
1.25V, then output RXFLAG is set = 1, otherwise
RXFLAG is set = 0. With the internal resistor of
50KΩ. By adding an external parallel resistor
between RXMON and GND, this threshold may be
increased.
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
6
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