ACS422x00
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
4.5. ADC Digital Filter .............................................................................................................................51
4.5.1. ADC Signal Path Control Register .....................................................................................53
4.5.2. ADC High Pass Filter Enable modes .................................................................................53
4.6. Digital ADC Volume Control .............................................................................................................53
4.6.1. ADC Digital Registers ........................................................................................................54
4.7. Automatic Level Control (ALC) ........................................................................................................54
4.7.1. ALC Operation ..................................................................................................................54
4.7.2. ALC Registers ....................................................................................................................56
4.7.3. Peak Limiter .......................................................................................................................57
4.7.4. Input Threshold ..................................................................................................................57
4.8. Digital Microphone Support .............................................................................................................57
4.8.1. DMIC Register ...................................................................................................................60
5. DIGITAL AUDIO AND CONTROL INTERFACES ................................................................... 61
5.1. Data Interface ..................................................................................................................................61
5.2. Master and Slave Mode Operation ..................................................................................................61
5.3. Audio Data Formats .........................................................................................................................62
5.4. Left Justified Audio Interface ...........................................................................................................62
5.5. Right Justified Audio Interface (assuming n-bit word length) ...........................................................62
5.6. I2S Format Audio Interface ..............................................................................................................63
5.7. Data Interface Registers ..................................................................................................................63
5.7.1. Audio Data Format Control Register ..................................................................................63
5.7.2. Audio Interface Output Tri-state .........................................................................................64
5.7.3. Audio Interface Bit Clock and LR Clock configuration ........................................................64
5.7.4. Bit Clock and LR Clock Mode Selection ............................................................................65
5.7.5. ADC Output Pin State ........................................................................................................66
5.7.6. Audio Interface Control 3 Register .....................................................................................66
5.8. Bit Clock Mode .................................................................................................................................66
5.9. Control Interface ..............................................................................................................................67
5.9.1. Register Write Cycle ..........................................................................................................67
5.9.2. Multiple Write Cycle ...........................................................................................................68
5.9.3. Register Read Cycle ..........................................................................................................68
5.9.4. Multiple Read Cycle ...........................................................................................................69
5.9.5. Device Addressing and Identification .................................................................................69
6. AUDIO CLOCK GENERATION ............................................................................................... 71
6.1. Internal Clock Generation (ACLK) ...................................................................................................71
6.1.1. External MCLK or XTAL .....................................................................................................71
6.1.2. REF Out .............................................................................................................................71
6.2. ACLK Clocking and Sample Rates ..................................................................................................71
6.3. DAC/ADC Modulator Rate Control ...................................................................................................72
7. PLL SECTION ........................................................................................................................ 74
7.1. PLL Block diagram ...........................................................................................................................74
7.2. PLL Defaults ....................................................................................................................................74
7.3. PLL Registers ..................................................................................................................................75
8. CHARACTERISTICS ............................................................................................................... 76
8.1. Electrical Specifications ...................................................................................................................76
8.1.1. Absolute Maximum Ratings ...............................................................................................76
8.1.2. Recommended Operating Conditions ................................................................................76
8.2. Device Characteristics .....................................................................................................................77
8.3. PLL Electrical Characteristics ..........................................................................................................79
9. REGISTER MAP ...................................................................................................................... 80
10. PIN INFORMATION ............................................................................................................... 82
10.1. ACS422A00 Pin Diagram ..............................................................................................................82
10.2. ACS422D00 Pin Diagram ..............................................................................................................83
10.3. Pin Tables ......................................................................................................................................84
10.3.1. Power Pins .......................................................................................................................84
10.3.2. Reference Pins ................................................................................................................84
10.3.3. Analog Input Pins .............................................................................................................85
10.3.4. Analog Output Pins ..........................................................................................................85
10.3.5. Data and Control Pins ......................................................................................................85
3
V1.6 08/13
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
ACS422X00
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