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ACS10D/SAMPLE PDF预览

ACS10D/SAMPLE

更新时间: 2022-12-01 19:48:38
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件
页数 文件大小 规格书
8页 107K
描述
AC SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

ACS10D/SAMPLE 数据手册

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ACS10MS  
Radiation Hardened  
Triple Three-Input NAND Gate  
April 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
• Total Dose 300K RAD (Si)  
• Single Event Upset (SEU) Immunity  
<1 x 10-10 Errors/Bit-Day (Typ)  
• SEU LET Threshold >80 MEV-cm2/mg  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 C1  
12 Y1  
11 C3  
10 B3  
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse  
A2  
B2  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range: 4.5V to 5.5V  
C2  
Y2  
9
8
A3  
Y3  
GND  
• Input Logic Levels  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
14 LEAD CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C  
TOP VIEW  
• Input Current 1µA at VOL, VOH  
A1  
B1  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
C1  
Y1  
Description  
A2  
The Intersil ACS10MS is a radiation hardened triple three-input  
NAND gate. A high on all inputs forces the output to a low state.  
B2  
C3  
B3  
A3  
Y3  
C2  
The ACS10MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of the  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
Y2  
GND  
8
Ordering Information  
PART NUMBER  
ACS10DMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
14 Lead SBDIP  
o
o
ACS10KMSR  
-55 C to +125 C  
14 Lead Ceramic Flatpack  
14 Lead SBDIP  
o
ACS10D/Sample  
ACS10K/Sample  
ACS10HMSR  
+25 C  
o
+25 C  
Sample  
14 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
Truth Table  
Functional Diagram  
INPUTS  
OUTPUT  
An  
An  
L
Bn  
L
Cn  
L
Yn  
H
H
H
H
H
H
H
L
(1, 3, 9)  
L
L
H
L
Bn  
Yn  
L
H
H
L
(2, 4, 10)  
(6, 8, 12)  
L
H
L
H
H
H
H
Cn  
(5, 11, 13)  
L
H
L
H
H
H
NOTE: L = Logic Level Low, H = Logic Level High  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518814  
File Number 3630  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1

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