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ACS109D/SAMPLE-03 PDF预览

ACS109D/SAMPLE-03

更新时间： 2024-01-14 01:23:14
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
2页 41K
描述
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16

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ACS109D/SAMPLE-03 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：AC
JESD-30 代码：R-CDIP-T16逻辑集成电路类型：J-K FLIP-FLOP
位数：2功能数量：2
端子数量：16输出极性：COMPLEMENTARY
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：25 ns认证状态：Not Qualified
座面最大高度：5.08 mm表面贴装：NO
技术：CMOS端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm

ACS109D/SAMPLE-03 数据手册

 浏览型号ACS109D/SAMPLE-03的Datasheet PDF文件第2页 
ACS109MS  
Data Sheet  
July 1999  
File Number 4760  
Radiation Hardened Dual J-K Flip-Flop  
with Set and Reset  
Features  
• QML Qualified Per MIL-PRF-38535 Requirements  
• 1.25 Micron Radiation Hardened SOS CMOS  
The Radiation Hardened ACS109MS is a Dual J-K Flip-  
Flop with Set and Reset. These Flip-Flops have  
independent J, K, Set, Reset, and Clock inputs and Q and  
Q outputs. The outputs change state on the positive-going  
transition of the clock. Set and Reset are accomplished  
asynchronously by Low-level inputs. All inputs are buffered  
and the outputs are designed for balanced propagation  
delay and transition times.  
• Radiation Environment  
- Latch-Up Free Under Any Conditions  
5
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10 RAD(Si)  
-10  
- SEU Immunity. . . . . . . . . . . . . <1 x 10  
Errors/Bit/Day  
2
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm )  
• Input Logic Levels. . . . V = (0.3)(V ), V = (0.7)(V  
IL CC IH  
)
CC  
The ACS109MS is fabricated on a CMOS Silicon on  
Sapphire (SOS) process, which provides an immunity to  
Single Event Latch-up and the capability of highly reliable  
performance in any radiation environment. These devices  
offer significant power reduction and faster performance  
when compared to ALSTTL types.  
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)  
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)  
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns (Max)  
Applications  
Specifications for Rad Hard QML devices are controlled  
by the Defense Supply Center in Columbus (DSCC). The  
SMD numbers listed below must be used when ordering.  
• High Speed Control Circuits  
• Sensor Monitoring  
• Low Power Designs  
Detailed Electrical Specifications for the ACS109MS are  
contained in SMD 5962-98632. A “hot-link” is provided  
on our homepage for downloading.  
http://www.intersil.com/spacedefense/spaceselect.htm  
Ordering Information  
INTERNAL MARKETING  
o
ORDERING NUMBER  
5962F9863201VCC  
NUMBER  
TEMP. RANGE ( C)  
PACKAGE  
16 Ld SBDIP  
DESIGNATOR  
CDIP2-T16  
CDIP2-T16  
CDFP4-F16  
CDFP4-F16  
NA  
ACS109DMSR-03  
-55 to 125  
ACS109D/SAMPLE-03  
5962F9863201VXC  
ACS109K/SAMPLE-03  
5962F9863201V9A  
ACS109D/SAMPLE-03  
ACS109KMSR-03  
25  
-55 to 125  
25  
16 Ld SBDIP  
16 Ld Flatpack  
16 Ld Flatpack  
Die  
ACS109K/SAMPLE-03  
ACS109HMSR-03  
25  
Pinouts  
ACS109MS  
ACS109MS  
(SBDIP)  
(FLATPACK)  
TOP VIEW  
TOP VIEW  
1R  
1J  
1
2
3
4
5
6
7
8
16  
V
1R  
1J  
1
2
3
4
5
6
7
8
16 V  
CC  
CC  
15  
14  
13  
12  
11  
10  
9
2R  
2J  
15 2R  
14 2J  
13 2K  
12 2CP  
11 2S  
10 2Q  
1K  
1K  
1CP  
1S  
2K  
2CP  
2S  
1CP  
1S  
1Q  
1Q  
1Q  
2Q  
2Q  
1Q  
GND  
9
2Q  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
12

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