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ACPL-M72U PDF预览

ACPL-M72U

更新时间: 2024-02-21 05:46:06
品牌 Logo 应用领域
安华高科 - AVAGO /
页数 文件大小 规格书
11页 103K
描述
Industrial CANBus communications interface

ACPL-M72U 数据手册

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ACPL-M71U and ACPL-M72U  
Wide Operating Temperature, High Speed, Low Power  
2
Digital Optocouplers with R Coupler™ Isolation  
Data Sheet  
Description  
Features  
The Avago ACPL-M71U and ACPL-M72U are high tem-  
perature, digital CMOS optocouplers in SOIC-5 packages.  
These optocouplers use the latest CMOS IC technology  
to achieve outstanding performance and very low power  
5 V CMOS compatible  
Common-Mode Rejection 40kV/s @ V =1000V:  
Wide Industrial temperature range: –40°C to 125°C  
CM  
consumption. All devices operate over the –40°C to 125 °C Low propagation delay :  
temperature range.  
– High Speed ACPL-M71U: 26ns @ I = 10 mA  
F
(Typical)  
The ACPL-M71U uses a high speed LED, and the  
ACPL-M72U uses a low current LED for lower power dis-  
– Low Power ACPL-M72U: 60ns @ I = 4 mA (Typical)  
F
sipation. The high speed ACPL-M71U featuring a 35 ns Worldwide safety approval:  
maximum propagation delay (I =10 mA). The ACPL-M72U  
F
– UL 1577 recognized, 3750 Vrms / 1 min  
– CSA approved  
– IEC/EN/DIN EN 60747-5-5  
optocoupler features very low power. With a low 4 mA  
LED drive current, ACPL-M72U typical propagation delay  
is 60 ns.  
Applications  
Each digital optocoupler has a CMOS detector IC, an in-  
tegrated photodiode, a high speed transimpedance  
amplifier, and a voltage comparator with an output  
driver.  
Industrial CANBus communications interface  
Industrial isolated high speed gate drivers for IGBTs  
and Power MOSFETs  
2
Avago R Coupler isolation products provide the rein-  
High temperature digital signal isolation  
Microcontroller interface  
forced insulation and reliability needed for critical in high  
temperature industrial applications  
Digital isolation for A/D and D/A conversion  
Functional Block Diagram  
ACPL-M71U/ACPL-M72U  
6
5
Vdd  
Vo  
1
3
Anode  
Truth Table  
LED Output (V )  
O
Cathode  
OFF  
ON  
H
L
Gnd  
4
Note: A 0.1 F bypass capacitor must be connected between pins 4 and 6.  
CAUTION: It is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by ESD.  

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