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AAT1162IRN-0.6-T1 PDF预览

AAT1162IRN-0.6-T1

更新时间： 2024-01-03 23:05:39
品牌 Logo 应用领域
思佳讯 - SKYWORKS 转换器稳压器开关式稳压器或控制器电源电路开关式控制器
页数 文件大小 规格书
19页 2637K
描述
12V, 1.5A Step-Down DC/DC Converter

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AAT1162IRN-0.6-T1 技术参数

是否Rohs认证： 符合生命周期：Obsolete
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
模拟集成电路 - 其他类型：SWITCHING REGULATOR控制模式：CURRENT-MODE
JESD-30 代码：R-PDSO-N16端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
最大输出电流：1.5 A封装主体材料：PLASTIC/EPOXY
封装代码：SON封装等效代码：SOLCC16,.12,18
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified子类别：Switching Regulator or Controllers
表面贴装：YES最大切换频率：1000 kHz
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.45 mm端子位置：DUAL
Base Number Matches：1

AAT1162IRN-0.6-T1 数据手册

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DATA SHEET  
AAT1162  
12V, 1.5A Step-Down DC/DC Converter  
Pin Descriptions  
Pin #  
Symbol Function  
Power switching node. LX is the drain of the internal P-channel switch and N-channel synchronous recti-  
fier. Connect the output inductor to the two LX pins and to EP2. A large exposed copper pad under the  
package should be used for EP2.  
1, 2, EP2  
3, 12  
LX  
N/C  
IN  
Not connected.  
Power source input. Connect IN to the input power source. Bypass IN to DGND with a 22μF or greater  
capacitor. Connect both IN pins together as close to the IC as possible. An additional 100nF ceramic  
capacitor should also be connected between the two IN pins and DGND, pin 6  
4, 5  
Exposed Pad 1 Digital Ground, DGND. The exposed thermal pad (EP1) should be connected to board  
ground plane and pins 6, 13, and 14. The ground plane should include a large exposed copper pad under  
the package for thermal dissipation (see package outline).  
Internal analog bias input. AIN supplies internal power to the AAT1162. Connect AIN to the input source  
voltage and bypass to AGND with a 0.1μF or greater capacitor. For additional noise rejection, connect to  
the input power source through a 10or lower value resistor.  
Internal LDO bypass node. The output voltage of the internal LDO is bypassed at LDO. The internal  
circuitry of the AAT1162 is powered from LDO. Do not draw external power from LDO. Bypass LDO to  
AGND with a 1μF or greater capacitor.  
Output voltage feedback input. FB senses the output voltage for regulation control. For fixed output  
versions, connect FB to the output voltage. For adjustable versions, drive FB from the output voltage  
through a resistive voltage divider. The FB regulation threshold is 0.6V.  
6, 13,  
14, EP1  
DGND  
AIN  
7
8
9
LDO  
FB  
10  
11  
COMP  
AGND  
Control compensation node. Connect a series RC network from COMP to AGND, R = 51k and C = 150pF.  
Analog signal ground. Connect AGND to PGND at a single point as close to the IC as possible.  
Active high enable input. Drive EN high to turn on the AAT1162; drive it low to turn it off. For automatic  
startup, connect EN to IN through a 4.7kresistor. EN must be biased high, biased low, or driven to a  
logic level by an external source. Do not let the EN pin float when the device is powered.  
15  
16  
EN  
PGND  
Power ground. Connect AGND to PGND at a single point as close to the IC as possible.  
Pin Configuration  
TDFN34-16  
(Top View)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
PGND  
EN  
LX  
LX  
EP2  
EP1  
N/C  
IN  
DGND  
DGND  
N/C  
IN  
AGND  
DGND  
AIN  
LDO  
COMP  
FB  
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com  
2
201998B  
• Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 20, 2013  
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