Wide Input Voltage, 2.4 MHz, 3.0 AAsynchronous Buck Regulator With
Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output
A8590
ELECTRICAL CHARACTERISTICS: valid at 4.0 V ≤ VIN ≤ 35 V; –40ºC ≤ TA = TJ ≤ 150ºC; unless otherwise specified.
Characteristics
Input Voltage
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Input Voltage Range1
VIN UVLO Start
VIN
4.0
3.6
3.2
–
–
35
4.0
3.6
–
V
V
VINUV(ON)
VINUV(OFF)
VINUV(HYS)
VIN rising
VIN falling
3.8
3.4
400
VIN UVLO Stop
V
VIN UVLO Hysteresis
Input Supply Current
mV
VSLEEP ≤ 0.5 V, TJ = 85ºC, VIN = 16 V
VSLEEP ≤ 0.5 V, TJ = 85ºC, VIN = 35 V
VBIAS > 3.2 V, IOUT = 0 mA
–
–
–
5
7
15
25
µA
µA
Sleep Mode Input Supply Current2,5
PWM Mode Input Supply Current2
IIN(SLEEP)
IIN(PWM)
ILO_IQ(1)
2.5
5.0
mA
VIN = 12 V, VOUT = 3.3 V, VPWMPFM ≤ 0.8 V,
IOUT = 40 µA, TA = 25ºC, components selected
per Table 3
–
–
–
–
–
–
50
µA
µA
µA
VIN = 12 V, VOUT = 5.0 V, VPWMPFM ≤ 0.8
V, IOUT = 200 µA, TA = 25ºC, components
selected per Table 3
Low-IQ PFM Input Supply Current2.3
250
750
VIN = 12 V, VOUT = 6.5 V, VPWMPFM ≤ 0.8 V,
IOUT = 1 mA, TA = 25ºC, components selected
per Table 3
Voltage Regulation
0ºC < TJ < 85ºC, VIN ≥ 4.1 V, VFB = VCOMP
–40ºC < TJ < 150ºC, VIN ≥ 4.1 V, VFB = VCOMP
792
788
800
800
808
812
mV
mV
Feedback Voltage Accuracy4
VFB
Low-IQ PFM Mode Output Voltage
Setting Range1,3
3.0 V < VBIAS < 5.5 V and ILO_IQ specifications
satisfied
VOUT(LO_IQ)
VOUT
3.3
0.8
–
–
6.5
10
–
V
V
V
PWM Output Voltage Setting Range3
VBIAS = GND, PWM only, no PFM mode
TA = 85°C, DCRLO ≤ 75 mΩ, VIN = 3.6 V, IOUT
=
3.27
3.295
1 A, fSW = 425 kHz
TA = 85°C, DCRLO ≤ 75 mΩ, VIN = 5.3 V, IOUT
1 A, fSW = 425 kHz
=
4.95
3.25
4.89
–
5.0
3.3
5.0
30
–
–
V
V
Output Dropout Voltage3
VOUT(SAT)
TA = 85°C, DCRLO ≤ 50 mΩ, VIN = 3.75 V, IOUT
= 1 A, fSW = 2 MHz
TA = 85°C, DCRLO ≤ 50 mΩ, VIN = 5.5 V, IOUT
1 A, fSW = 2 MHz
=
–
V
8 V < VIN < 12 V, components selected per
Table 3
Low-IQ PFM Mode Ripple Voltage3
ΔVOUT(LO_IQ)
IPEAK(LO_IQ)
IOUT(LO_IQ)
65
mVPP
fSW < 750 kHz
fSW < 750 kHz
–
–
750
850
–
–
mAPEAK
mAPEAK
Low-IQ PFM Mode Peak Current
Threshold
Maximum load to maintain ΔVOUT(LO_IQ)
components selected per Table 3
,
Low-IQ PFM Mode DC Load Current3
400
550
700
mA
Continued on next page...
1Thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.
2Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
3Ensured by design and characterization, not production tested.
4Performance at the 0°C and 85°C ranges ensured by design and characterization, not production tested.
5Performance at 85°C ensured by design and characterization, not production tested.
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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