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A8287SLB

更新时间： 2024-01-08 07:00:23
品牌 Logo 应用领域
急速微 - ALLEGRO 稳压器模拟IC信号电路光电二极管
页数 文件大小 规格书
17页 526K
描述
LNB Supply and Control Voltage Regulator

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A8287SLB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：BATWING, LEAD FREE, PLASTIC, SOIC-24针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：15.29 mm湿度敏感等级：3
功能数量：1端子数量：24
最高工作温度：85 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：10/16 V认证状态：Not Qualified
座面最大高度：2.64 mm子类别：Power Management Circuits
最大供电电流 (Isup)：7 mA最大供电电压 (Vsup)：16 V
最小供电电压 (Vsup)：10 V标称供电电压 (Vsup)：12 V
表面贴装：YES温度等级：OTHER
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

A8287SLB 数据手册

 浏览型号A8287SLB的Datasheet PDF文件第4页浏览型号A8287SLB的Datasheet PDF文件第5页浏览型号A8287SLB的Datasheet PDF文件第6页浏览型号A8287SLB的Datasheet PDF文件第8页浏览型号A8287SLB的Datasheet PDF文件第9页浏览型号A8287SLB的Datasheet PDF文件第10页 
A8285/A8287  
LNB Supply and Control Voltage Regulator  
this feature is disabled and the device is not turned off dur-  
ing an overcurrent.  
• Undervoltage Lockout (VUV). When the input voltage  
(VIN) drops below the undervoltage threshold, the undervolt-  
age bit VUV is set, disabling the output.  
Status Register. The status of the A8285/A8287 read reg-  
ister can be interrogated by the system master controller via  
the I2C interface. Status functions include the following:  
When VIN is initially applied to the A8285/A8285, the VUV bit  
is set, indicating that an undervoltage condition has occurred.  
• Power Not Good (PNG). When the LNB output is enabled,  
and the LNB output is below 85% of the programmed LNB  
voltage, the PNG bit is set.  
IRQ Flag. The IRQ flag is activated when any fault con-  
dition occurs, including: thermal shutdown, overcurrent,  
undervoltage, or the occurrence of a power-up sequence.  
Note that the IRQ flag is not activated when either (a) the  
channel is disabled (DIS), as it may have been disabled  
intentionally by the master controller, or (b) if PNG is active,  
as the A8285/A8287 may be starting up. Fault conditions are  
stored in the status registers. Also note that the IRQ flag will  
not activate when an overcurrent occurs and ODT is dis-  
• Disable (DIS). Provides the status of the LNB output.  
When set, this indicates that the output is disabled, either  
intentionally or by a fault.  
• Thermal Shutdown (TSD). When the junction tempera-  
ture exceeds the maximum threshold, the thermal shutdown  
bit is set, which disables the LNB output. DIS also is set.  
abled. In this condition, the device operates within ILIM  
.
• Overcurrent (OCP). This disables LNB output when an  
overcurrent appears on the LNB output for a period greater  
than the ODT (ODT must be enabled for this feature to take  
effect). In addition, the DIS bit is set. Note: If an overcurrent  
occurs and ODT is disabled, the A8285/A8287 will operate  
in current limit indefininitely and the OCP bit will not be set.  
When the IRQ flag is activated during either of the above  
fault conditions, and the system master controller addresses  
the A8285/A8287 with the read/write bit set to 1, then the  
IRQ flag is reset once the A8285/A8287 acknowledges the  
address. When the master controller reads the data and is  
acknowledged, the status registers are updated. If the fault  
is removed, the A8285/A8287 is again ready for operation  
(being re-enabled via a write command). Otherwise, the  
controller can keep polling the A8285/A8287 until the fault  
is removed.  
Output Voltage Amplitude Selection Table  
VSEL3  
VSEL2  
VSEL1  
VSEL0  
LNB (V)  
12.709  
13.042  
13.375  
13.709  
14.042  
14.375  
14.709  
15.042  
18.042  
18.375  
18.709  
19.042  
19.375  
19.709  
20.042  
20.375  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
When VIN, is initially applied to the A8285/A8285, the I2C  
interface will not function until the internal logic supply VREG  
has reached its operating level. Once VREG is within toler-  
ance, the VUV bit in the status register is set and the IRQ is  
activated to inform the master controller of this condition.  
(The IRQ is effectively acting as a power-up flag.) The IRQ  
is reset when the A8285/A8287 acknowledges the address.  
Once the master has read the status registers, the VUV bit is  
reset. The device is then ready for operation.  
I2C Interface. This is a serial interface that uses two bus  
lines, SCL and SDA, to access the internal Control and  
Status registers of the A8285/A8287. Data is exchanged  
between a microcontroller (master) and the A8285/A8287  
(slave). The clock input to SCL is generated by the master,  
while SDA functions as either an input or an open drain  
output, depending on the direction of the data.  
7
www.allegromicro.com  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
1...45678910...17

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