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A80186

更新时间： 2024-01-07 02:34:08
品牌 Logo 应用领域
英特尔 - INTEL 微控制器和处理器外围集成电路微处理器时钟
页数 文件大小 规格书
33页 396K
描述
HIGH-INTEGRATION 16-BIT MICROPROCESSORS

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A80186 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：PGA
包装说明：PGA,针数：68
Reach Compliance Code：unknown风险等级：5.54
地址总线宽度：20位大小：16
边界扫描：NO最大时钟频率：16 MHz
外部数据总线宽度：16格式：FIXED POINT
集成缓存：NOJESD-30 代码：S-CPGA-P68
JESD-609代码：e0长度：29.464 mm
低功率模式：NO端子数量：68
最高工作温度：70 °C最低工作温度：
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：PGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：5.21 mm速度：8 MHz
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：PIN/PEG
端子节距：2.54 mm端子位置：PERPENDICULAR
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：29.464 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR

A80186 数据手册

 浏览型号A80186的Datasheet PDF文件第3页浏览型号A80186的Datasheet PDF文件第4页浏览型号A80186的Datasheet PDF文件第5页浏览型号A80186的Datasheet PDF文件第7页浏览型号A80186的Datasheet PDF文件第8页浏览型号A80186的Datasheet PDF文件第9页 
80186/80188  
Table 1. Pin Descriptions (Continued)  
Pin  
Symbol  
Type  
Name and Function  
No.  
A19/S6  
A18/S5  
A17/S4  
A16/S3  
65  
66  
67  
68  
O
O
O
O
Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most  
significant address bits during T . These signals are active HIGH. During T , T , T ,  
W
and T , the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a  
4
DMA-initiated bus cycle. During the same T-states, S3, S4, and S5 are always LOW.  
The status pins float during bus HOLD or RESET.  
1
2
3
AD15 (A15)  
AD14 (A14)  
AD13 (A13)  
AD12 (A12)  
1
3
5
7
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Address/Data Bus signals constitute the time multiplexed memory or I/O address (T )  
1
and data (T , T , T , and T ) bus. The bus is active HIGH. A is analogous to BHE for  
2
3
W
4
0
the lower byte of the data bus, pins D through D . It is LOW during T when a byte is  
1
7
0
to be transferred onto the lower portion of the bus in memory or I/O operations. BHE  
does not exist on the 80188, as the data bus is only 8 bits wide.  
AD11 (A11) 10  
AD10 (A10) 12  
AD9 (A9)  
AD8 (A8)  
AD7  
14  
16  
2
AD6  
4
AD5  
6
AD4  
8
AD3  
11  
13  
15  
17  
AD2  
AD1  
AD0  
BHE/S7  
(S7)  
64  
O
During T the Bus High Enable signal should be used to determine if data is to be  
1
enabled onto the most significant half of the data bus; pins D –D . BHE is LOW  
15  
8
during T for read, write, and interrupt acknowledge cycles when a byte is to be  
1
transferred on the higher half of the bus. The S status information is available during  
7
T , T , and T . S is logically equivalent to BHE. BHE/S7 floats during HOLD. On the  
2
3
4
80188, S7 is high during normal operation.  
7
BHE and A0 Encodings (80186 Only)  
Function  
BHE  
A0  
Value Value  
0
0
1
1
0
1
0
1
Word Transfer  
Byte Transfer on upper half of data bus (D15–D8)  
Byte Transfer on lower half of data bus (D –D )  
7
0
Reserved  
ALE/QS0  
WR/QS1  
61  
63  
O
O
Address Latch Enable/Queue Status 0 is provided by the processor to latch the  
address. ALE is active HIGH. Addresses are guaranteed to be valid on the trailing  
edge of ALE. The ALE rising edge is generated off the rising edge of the CLKOUT  
immediately preceding T of the associated bus cycle, effectively one-half clock cycle  
1
earlier than in the 8086. The trailing edge is generated off the CLKOUT rising edge in  
T
as in the 8086. Note that ALE is never floated.  
1
Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a  
memory or an I/O device. WR is active for T , T , and T of any write cycle. It is active  
2
3
W
LOW, and floats during HOLD. When the processor is in queue status mode, the ALE/  
QS0 and WR/QS1 pins provide information about processor/instruction queue  
interaction.  
QS1  
QS0  
Queue Operation  
0
0
1
1
0
1
1
0
No queue operation  
First opcode byte fetched from the queue  
Subsequent byte fetched from the queue  
Empty the queue  
NOTE:  
Pin names in parentheses apply to the 80188.  
6
6
1...3456789...33

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