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A6821

更新时间： 2024-01-15 03:13:25
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器
页数 文件大小 规格书
9页 220K
描述
DABiC-5 8-Bit Serial Input Latched Sink Drivers

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A6821 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：LEAD FREE, MS-013AA, SOIC-16
针数：16Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.81驱动器位数：8
接口集成电路类型：SIPO BASED PERIPHERAL DRIVERJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
湿度敏感等级：3功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-20 °C输出电流流向：SINK
最大输出电流：0.35 A封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：3.3/5 V认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Peripheral Drivers
最大供电电压：5.5 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：BIMOS温度等级：OTHER
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

A6821 数据手册

 浏览型号A6821的Datasheet PDF文件第1页浏览型号A6821的Datasheet PDF文件第2页浏览型号A6821的Datasheet PDF文件第3页浏览型号A6821的Datasheet PDF文件第5页浏览型号A6821的Datasheet PDF文件第6页浏览型号A6821的Datasheet PDF文件第7页 
A6821  
DABiC-5 8-Bit Serial Input Latched Sink Drivers  
Timing Requirements and Specifications  
(Logic Levels are VDD and Ground)  
C
50%  
CLOCK  
A
B
SERIAL  
DATA IN  
DATA  
50%  
t
p(CH-SQX)  
SERIAL  
DATA OUT  
DATA  
50%  
D
E
50%  
STROBE  
OUTPUT ENABLE  
LOW = ALL OUTP UTS E NABLE D  
t
p(STH-QH)  
t
p(STH-QL)  
90%  
DATA  
OUT  
N
10%  
HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D)  
50%  
OUTPUT ENABLE  
t
en(BQ)  
t
t
f
r
t
90%  
50%  
dis(BQ)  
OUT  
DATA  
N
10%  
Key  
A
Description  
Symbol  
tsu(D)  
Time (ns)  
Data Active Time Before Clock Pulse (Data Set-Up Time)  
Data Active Time After Clock Pulse (Data Hold Time)  
Clock Pulse Width  
25  
25  
th(D)  
B
tw(CH)  
tsu(C)  
C
50  
D
Time Between Clock Activation and Strobe  
Strobe Pulse Width  
100  
50  
tw(STH)  
E
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be  
attainable; operation at high temperatures will reduce the specified maxi-  
mum clock frequency.  
Information present at any register is transferred to the respective latch  
when the STROBE is high (serial-to-parallel conversion). The latches will  
continue to accept new data as long as the STROBE is held high. Applica-  
tions where the latches are bypassed (STROBE tied high) will require that  
the OUTPUT ENABLE input be high during serial data entry.  
Powering-on with the inputs in the low state ensures that the registers and  
latches power-on in the low state (POR).  
Serial Data present at the input is transferred to the shift register on the logical  
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK  
pulses, the registers shift data information towards the SERIAL DATA OUT-  
PUT. The SERIAL DATA must appear at the input prior to the rising edge of the  
CLOCK input waveform.  
When the OUTPUT ENABLE input is high, all of the output buffers are  
disabled (OFF). The information stored in the latches or shift register is not  
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE  
input low, the outputs are controlled by the state of their respective latches.  
4
www.allegromicro.com  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
1234567...9

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