6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
B
CLOCK
A
SERIAL
DATA IN
DATA
50%
t
p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
E
50%
STROBE
BLANKING
LOW = ALL OUTPUTS ENABLED
t
p(STH-QH)
t
p(STH-QL)
90%
DATA
OUT
N
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
BLANKING
t
dis(BQ)
t
t
t
f
en(BQ)
r
90%
OUT
N
DATA
10%
Dwg. WP-030
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................... 25 ns
C. Clock Pulse Width, tw(CH) ............................................... 50 ns
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns
E. Strobe Pulse Width, tw(STH) ............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
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