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A6810SLWTR-T

更新时间： 2024-01-08 01:03:21
品牌 Logo 应用领域
急速微 - ALLEGRO 显示驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
9页 337K
描述
10-Bit Serial Input Latched Source Driver

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A6810SLWTR-T 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP20,.4
针数：20Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.82其他特性：CAN ALSO OPERATE WITH 5V LOGIC SUPPLY
数据输入模式：SERIAL接口集成电路类型：VACUUM FLUORESCENT DISPLAY DRIVER
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：12.8 mm湿度敏感等级：3
复用显示功能：NO功能数量：1
区段数：10端子数量：20
最高工作温度：85 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3.3/5,60 V认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Display Drivers
最大压摆率：3 mA最大供电电压：5.5 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-Nom：60 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：7.5 mm
最小 fmax：10 MHzBase Number Matches：1

A6810SLWTR-T 数据手册

 浏览型号A6810SLWTR-T的Datasheet PDF文件第3页浏览型号A6810SLWTR-T的Datasheet PDF文件第4页浏览型号A6810SLWTR-T的Datasheet PDF文件第5页浏览型号A6810SLWTR-T的Datasheet PDF文件第7页浏览型号A6810SLWTR-T的Datasheet PDF文件第8页浏览型号A6810SLWTR-T的Datasheet PDF文件第9页 
A6810  
10-Bit Serial Input Latched Source Driver  
TIMING REQUIREMENTS and SPECIFICATIONS  
(Logic Levels are VDD and Ground)  
C
50%  
CLOCK  
A
B
SERIAL  
DATA IN  
DATA  
50%  
t
p(CH-SQX)  
SERIAL  
DATA OUT  
DATA  
50%  
D
E
50%  
STROBE  
BLANKING  
LOW = ALL OUTPUTS ENABLED  
t
p(STH-QH)  
t
p(STH-QL)  
90%  
DATA  
OUT  
N
10%  
Dwg. WP-029  
HIGH = ALL OUTPUTS BLANKED (DISABLED)  
50%  
BLANKING  
OUT  
t
dis(BQ)  
t
t
f
r
t
90%  
50%  
en(BQ)  
DATA  
N
10%  
Dwg. WP-030A  
A. Data Active Time Before Clock Pulse  
(Data Set-Up Time), tsu(D) ........................................... 25 ns  
B. Data Active Time After Clock Pulse  
SERIAL DATA must appear at the input prior to the rising edge  
of the CLOCK input waveform.  
(Data Hold Time), th(D) ................................................ 25 ns  
C. Clock Pulse Width, tw(CH) ................................................. 50 ns  
Information present at any register is transferred to the  
respective latch when the STROBE is high (serial-to-parallel  
conversion). The latches will continue to accept new data as  
long as the STROBE is held high. Applications where the  
latches are bypassed (STROBE tied high) will require that the  
BLANKING input be high during serial data entry.  
D. Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns  
E. Strobe Pulse Width, tw(STH) .............................................. 50 ns  
NOTE – Timing is representative of a 10 MHz clock. Higher  
speeds may be attainable; operation at high temperatures will  
reduce the specified maximum clock frequency.  
When the BLANKING input is high, the output source  
drivers are disabled (OFF); the PNP active pull-down sink  
drivers are ON. The information stored in the latches is not  
affected by the BLANKING input. With the BLANKING input  
low, the outputs are controlled by the state of their respective  
latches.  
Serial Data present at the input is transferred to the shift  
register on the logic “0” to logic “1” transition of the CLOCK  
input pulse. On succeeding CLOCK pulses, the registers shift  
data information towards the SERIAL DATA OUTPUT. The  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
5
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
1...3456789

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