A61L6316 Series
64K X 16 BIT HIGH SPEED CMOS SRAM
Features
General Description
n Center power pinout
n Supply voltage: -10: 3.3V+10%, -5%
-12, -15: 3.3V±10%
n Access times: 10/12/15 ns (max.)
n Current: Operating: -10: 230mA (max)
-12: 220mA (max.)
The A61L6316 is a high speed 1,048,576-bit static
random access memory organized as 65,536 words by 16
bits and operates on low power supply voltage from 3.0V
to 3.6V. It is built using AMIC’s high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
-15: 210mA (max.)
Standby: TTL: 25mA (max.)
CMOS: 12mA (max.)
n Extended operating temperature range: -25°C to 85°C
for -I series
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 44-pin 400mil SOJ and 44-pin 400mil
TSOP(II) forward packages.
The chip enable input is provided for POWER-DOWN, to
disable the device. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Product Family
Power Dissipation
Package
Operating
Temperature
VCC Range
Product
Family
Speed
Data Retention
(ICCDR, Typ.)
Standby
Type
(ISB1, Typ.)
44L SOP
44L TSOP(II)
0°C ~ +70°C
-25°C ~ +85°C
A61L6316
3.0V ~ 3.6V
10/12/15 ns
3mA
5mA
1. Typical values are measured at VCC = 3.3V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configuration
n SOJ / TSOP (II)
A0
A1
1
2
3
4
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A15
A14
A13
OE
A2
A3
A4
5
HB
CE
6
LB
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A12
A11
A10
A9
A6
A7
A8
NC
NC
(July, 2002, Version 1.1)
1
AMIC Technology, Inc.