Datasheet > A5977GLPTR-T

A5977GLPTR-T

更新时间： 2022-02-26 14:09:16

品牌	Logo	应用领域
急速微 - ALLEGRO		/
页数	文件大小	规格书
16页	622K
描述
Microstepping DMOS Driver with Translator

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数据手册

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A5977GLPTR-T 数据手册

A5977

Microstepping DMOS Driver with Translator

PINOUT DIAGRAM AND TERMINAL LIST TABLE

Terminal List Table

SENSE1

VBB1

Number

Name

SENSE1

HOMEn

DIR

Description

HOMEn

DIR

SLEEPn

ENABLEn

OUT1B

CP2

Sense resistor for bridge 1

Logic output

OUT1A

PFD

Logic input

RC1

CP1

OUT1A

PFD

DMOS full-bridge 1, output A

Analog input for mixed-decay setting

Analog input for fixed off-time, bridge 1

Analog ground

PAD

AGND

REF

VCP

PGND

VREG

STEP

OUT2B

RESETn

RC1

RC2

VDD

AGND*

REF

OUT2A

MS2

Gm reference input

Analog input for fixed off-time, bridge 2

Logic supply voltage

DMOS full-bridge 2, output A

Logic input

RC2

MS1

SENSE2

VBB2

–

VDD

OUT2A

MS2

Package LP,

28-Pin TSSOP

MS1

Logic input

SENSE2

VBB2

Sense resistor for bridge 2

Load supply for bridge 2

Logic input

RESETn

OUT2B

STEP

VREG

PGND*

VCP

Logic input

DMOS full-bridge 2, output B

Logic input

Regulator decoupling

Power ground

Reservoir capacitor

Charge pump capacitor

DMOS full-bridge 1, output B

Logic input

CP1

CP2

OUT1B

ENABLEn

SLEEPn

VBB1

PAD*

Logic input

Load supply for bridge 1

Thermal pad

* GND, PGND, and thermal pad must be connected together externally under the device.

Allegro MicroSystems, LLC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

1 234 5 6 7...16

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