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A4987

更新时间： 2024-02-09 13:44:25
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器
页数 文件大小 规格书
16页 441K
描述
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection

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A4987 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC24,.16SQ,20针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.61
模拟集成电路 - 其他类型：STEPPER MOTOR CONTROLLERJESD-30 代码：S-XQCC-N24
JESD-609代码：e3长度：4 mm
湿度敏感等级：2功能数量：1
端子数量：24最高工作温度：85 °C
最低工作温度：-20 °C最大输出电流：1 A
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：35 V认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Motion Control Electronics
最大供电电流 (Isup)：4 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：NMOS
温度等级：OTHER端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：4 mmBase Number Matches：1

A4987 数据手册

 浏览型号A4987的Datasheet PDF文件第10页浏览型号A4987的Datasheet PDF文件第11页浏览型号A4987的Datasheet PDF文件第12页浏览型号A4987的Datasheet PDF文件第13页浏览型号A4987的Datasheet PDF文件第14页浏览型号A4987的Datasheet PDF文件第15页 
DMOS Dual Full-Bridge PWM Motor Driver  
with Overcurrent Protection  
A4987  
LP Package, 24-Pin TSSOP with Exposed Thermal Pad  
0.65  
7.80 ±0.10  
0.45  
4° ±4  
24  
+0.05  
0.15  
–0.06  
B
3.00  
6.10  
3.00 4.40 ±0.10 6.40 ±0.20  
0.60 ±0.15  
(1.00)  
A
1
2
4.32  
0.25  
1.65  
4.32  
24X  
C
SEATING PLANE  
GAUGE PLANE  
SEATING  
PLANE  
C
PCB Layout Reference View  
0.10  
C
+0.05  
–0.06  
0.25  
0.65  
1.20 MAX  
0.15 MAX  
For reference only  
(reference JEDEC MO-153 ADT)  
Dimensions in millimeters  
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions  
Exact case and lead configuration at supplier discretion within limits shown  
Terminal #1 mark area  
A
B
C
Exposed thermal pad (bottom surface)  
Reference land pattern layout (reference IPC7351  
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all  
adjacent pads; adjust as necessary to meet application process  
requirements and PCB layout tolerances; when mounting on a multilayer  
PCB, thermal vias at the exposed thermal pad land can improve thermal  
dissipation (reference EIA/JEDEC Standard JESD51-5)  
Copyright ©2009-2010, Allegro MicroSystems, Inc.  
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.  
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-  
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the  
information being relied upon is current.  
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the  
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.  
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;  
nor for any infringement of patents or other rights of third parties which may result from its use.  
For the latest version of this document, visit our website:  
www.allegromicro.com  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff, Box 15036  
16  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
www.allegromicro.com  
1...13141516

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