A4987SLPTR-T

更新时间： 2024-01-02 05:02:18

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动器
页数	文件大小	规格书
16页	441K
描述
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection

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A4987SLPTR-T 数据手册

A4987

DMOS Dual Full-Bridge PWM Motor Driver

with Overcurrent Protection

Features and Benefits

▪ Low R_DS(ON)outputs

Description

The A4987 is a dual DMOS full-bridge stepper motor driver

▪ Internal mixed current decay mode

▪ Synchronous rectification for low power dissipation

▪ Internal UVLO

withparallelinputcommunicationandovercurrentprotection.

Eachfull-bridgeoutputisratedupto35Vand±1A.TheA4987

includesfixedoff-timepulsewidthmodulation(PWM)current

regulators,alongwith2-bitnonlinearDACs(digital-to-analog

converters) that allow stepper motors to be controlled in full,

half, and quarter steps. The PWM current regulator uses the

Allegro^®patented mixed decay mode for reduced audible

motor noise, increased step accuracy, and reduced power

dissipation.

▪ Crossover-current protection

▪ 3.3 and 5 V compatible logic supply

▪ Thin profile QFN and TSSOP packages

▪ Thermal shutdown circuitry

▪ Short-to-ground protection

▪ Shorted load protection

▪ Low current Sleep mode, < 10 μA

Internalsynchronousrectificationcontrolcircuitryisprovided

to improve power dissipation during PWM operation.

The outputs are protected from shorted load and short-to-

groundevents,whichprotectthedriverandassociatedcircuitry

from thermal damage or flare-ups. Other protection features

includethermalshutdownwithhysteresis,undervoltagelockout

(UVLO) and crossover current protection. Special power-up

sequencing is not required.

Packages:

Approximate size

24-contact QFN

with exposed thermal pad

4 mm × 4 mm × 0.75 mm

(ES package)

TheA4987issuppliedintwopackages,a24-contactQFN(ES)

anda24-pinTSSOP(LP).Bothpackageshaveexposedthermal

pads for enhanced thermal performance. The 24-contact ES is

4 mm × 4 mm, with a nominal overall package height of 0.75

mm. The 24-pin LP is a TSSOP with 0.65 pitch and an overall

package height of ≤1.2 mm. Both packages are lead (Pb) free,

with 100% matte tin leadframe plating.

24-pin TSSOP

with exposed thermal pad

(LP Package)

Typical Application Diagram

V_DD

0.1 μF

0.22 μF

VREG ROSC CP1

VDD

CP2 VCP

VBB1

VBB2

0.22 μF

100 μF

Microcontroller or

Controller Logic

OUT1A

SLEEP

IN01

A4987

OUT1B

SENSE1

IN02

PH1

IN11

IN12

PH2

OUT2A

OUT2B

SENSE2

VREF

GND

4987-DS

12 3 4 5 6 7...16

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