Datasheet > A43E16161V-75UF

A43E16161V-75UF

更新时间： 2022-11-25 21:08:16

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
46页	1315K
描述
1M X 16 Bit X 2 Banks Low Power Synchronous DRAM

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数据手册

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A43E16161V-75UF 数据手册

A43E16161

Preliminary

1M X 16 Bit X 2 Banks Low Power Synchronous DRAM

Features

ꢀLow power supply

ꢀ64ms refresh period (4K cycle)

- VDD: 1.8V VDDQ : 1.8V

ꢀLVCMOS compatible with multiplexed address

ꢀSelf refresh with programmable refresh period through

EMRS cycle

ꢀProgrammable Power Reduction Feature by partial

array activation during Self-refresh through EMRS

cycle

ꢀTwo banks / Pulse RAS

ꢀMRS cycle with address key programs

- CAS Latency (2 & 3)

- Burst Length (1,2,4,8 & full page)

- Burst Type (Sequential & Interleave)

ꢀAll inputs are sampled at the positive going edge of the

system clock

ꢀAuto TCSR

ꢀIndustrial operating temperature range: -40ºC to +85ºC

for -U series.

ꢀAvailable in 54-pin TSOP(II) package

ꢀPackage is available to lead free (-F series)

ꢀDeep Power Down Mode

ꢀDQM for masking

ꢀAuto & self refresh

ꢀClock Frequency (max) : 105MHz @ CL=3 (-95)

133MHz @ CL=3 (-75)

General Description

The A43E16161 is 33,554,432 bits Low Power

synchronous high data rate Dynamic RAM organized as 2

X 1,048,576 words by 16 bits, fabricated with AMIC’s high

performance CMOS technology. Synchronous design

allows precise cycle control with the use of system clock.

I/O transactions are possible on every clock cycle. Range

of operating frequencies, programmable latencies allows

the same device to be useful for a variety of high

bandwidth,

high

performance

memory

system

applications.

Pin Configuration

ꢀ54 TSOP (II)

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

A43E16161V

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

PRELIMINARY

(August, 2005, Version 0.0)

AMIC Technology, Corp.

123 4 5 6 7...46

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