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A3979 PDF预览

A3979

更新时间: 2024-02-28 18:04:15
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器
页数 文件大小 规格书
14页 330K
描述
Microstepping DMOS Driver with Translator

A3979 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:HTSSOP, TSSOP28,.25针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.13
模拟集成电路 - 其他类型:STEPPER MOTOR CONTROLLERJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:9.7 mm
湿度敏感等级:2功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-20 °C最大输出电流:2.5 A
封装主体材料:PLASTIC/EPOXY封装代码:HTSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3/5,35 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Motion Control Electronics
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:NMOS温度等级:OTHER
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

A3979 数据手册

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A3979  
DMOS Microstepping Driver with Translator  
Functional Description  
Device Operation. The A3979 is a complete micro-  
Step Input (STEP). A low-to-high transition on the  
STEP input sequences the translator and advances the motor  
one increment. The translator controls the input to the DACs  
and the direction of current flow in each winding. The size  
of the increment is determined by the combined state of  
inputs MS1 and MS2 (see table 1).  
stepping motor driver with a built-in translator for easy  
operation with minimal control lines. It is designed to  
operate bipolar stepper motors in full-, half-, quarter-, and  
sixteenth-step modes. The currents in each of the two output  
full-bridges (all of the N-channel MOSFETs) are regulated  
with fixed off-time PMW (pulse width modulated) control  
circuitry. At each step, the current for each full-bridge is  
set by the value of its external current-sense resistor (RS1  
or RS2), a reference voltage (VREF), and the output voltage  
of its DAC (which in turn is controlled by the output of the  
translator).  
Microstep Select (MS1 and MS2). The input on  
terminals MS1 and MS2 selects the microstepping format,  
as shown in table 1. Any changes made to these inputs do not  
take effect until the next rising edge of a step command signal  
on the STEP input.  
Direction Input (DIR). The state of the DIR input deter-  
mines the direction of rotation of the motor. Any changes  
made to this input does not take effect until the next rising  
edge of a step command signal on the STEP input.  
At power-on or reset, the translator sets the DACs and the  
phase current polarity to the initial Home state (shown in  
figures 2 through 5), and the current regulator to Mixed  
decay mode for both phases. When a step command signal  
occurs on the STEP input, the translator automatically  
sequences the DACs to the next level and current polarity.  
(See table 2 for the current-level sequence.) The microstep  
resolution is set by the combined effect of inputs MS1 and  
MS2, as shown in table 1.  
Internal PWM Current Control. Each full bridge is  
controlled by a fixed–off-time PWM current-control circuit  
that limits the load current to a desired value, ITRIP. Initially,  
a diagonal pair of source and sink MOS outputs are enabled  
and current flows through the motor winding and the current  
sense resistor, RSx. When the voltage across RSx equals the  
DAC output voltage, the current-sense comparator resets the  
PWM latch. The latch then turns off either the source MOS-  
FETs (when in Slow decay mode) or the sink and source  
MOSFETs (when in Fast or Mixed decay mode).  
While stepping is occurring, if the next output level of the  
DACs is lower than the immediately preceeding output  
level, then the decay mode (Fast, Slow, or Mixed) for the  
active full bridge is set by the PFD input. If the next DAC  
output level is higher than or equal to the preceeding level,  
then the decay mode for that full bridge will be Slow decay.  
This automatic current-decay selection improves microstep-  
ping performance by reducing the distortion of the current  
waveform due to back EMF of the motor.  
The maximum value of current limiting is set by the selec-  
tion of RS and the voltage at the VREF input with a transcon-  
ductance function approximated by:  
ITRIPmax = VREF/8RS  
RESET Input ( ¯R¯¯E¯¯S¯¯E¯¯T¯). The R¯¯E¯¯S¯E¯¯T¯¯ input (active  
low) sets the translator to a predefined Home state (shown  
in figures 2 through 5), and turns off all of the DMOS out-  
puts. The HOME output goes low and all STEP inputs are  
The DAC output reduces the VREF output to the cur-  
rent-sense comparator in precise steps (see table 2 for  
% ITRIPmax at each step).  
ITRIP = (% ITRIPmax/100) ITRIPmax  
ignored until the ¯R¯E¯¯S¯E¯¯T¯¯ input is set to high.  
It is critical that the maximum rating (0.5 V) on either the  
SENSE1 and SENSE2 pins is not exceeded. For full step-  
ping, VREF can be applied up to the maximum rating of VDD  
because the peak sense value is 0.707 × VREF /8. In all other  
modes, VREF should not exceed 4 V.  
Home Output (HOME). The HOME output is a logic  
output indicator of the initial state of the translator. At  
power-on, the translator is reset to the Home state (shown in  
figures 2 through 5).  
Allegro MicroSystems, Inc.  
7
115 Northeast Cutoff, Box 15036  
26184.23  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
www.allegromicro.com  

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