A3979
Microstepping DMOS Driver with Translator
Features and Benefits
▪ ±2.5 A, 35 V output rating
Description
The A3979 is a complete microstepping motor driver with
▪ Low RDS(On) outputs: 0.28 Ω source, 0.22 Ω sink, typical
▪ Automatic current decay mode detection/selection
▪ 3.0 to 5.5 V logic supply voltage range
▪ Slow, Fast or Mixed current decay modes
▪ Home output
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection
built-intranslator,designedasapin-compatiblereplacementfor
the successfulA3977, with enhanced microstepping ( /16 step)
1
precision. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and sixteenth-step modes, with an output
drive capacity of up to 35 V and ±2.5A. TheA3979 includes a
fixedoff-timecurrentregulatorthathastheabilitytooperatein
Slow, Fast, or Mixed decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3979. It allows the simple input of one pulse on the STEP
pin to drive the motor one microstep, which can be either a full
step, half, quarter, or sixteenth, depending on the setting of the
MS1andMS2logicinputs.Therearenophase-sequencetables,
high-frequencycontrollines,orcomplexinterfacestoprogram.
The A3979 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
Package: 28 lead TSSOP (suffix LP) with
exposed thermal pad
Internalsynchronous-rectificationcontrolcircuitryisprovided
to improve power dissipation during PWM operation. Internal
circuit protection includes: thermal shutdown with hysteresis,
UVLO (undervoltage lockout), and crossover-current
protection. Special power-on sequencing is not required.
The A3979 is supplied in a low-profile (height ≤1.20 mm),
28-pin TSSOP with exposed thermal pad. The package is lead
(Pb) free, with 100% matte tin leadframe plating.
Not to scale
Pin-out Diagram
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SENSE1
HOME
DIR
VBB1
SLEEP
ENABLE
OUT1B
CP2
3
4
OUT1A
PFD
5
PWM
Timer
Charge
Pump
6
RC1
CP1
Translator
and
Control
Logic
7
AGND
REF
VCP
8
÷8
PGND
VREG
STEP
OUT2B
RESET
SR
9
RC2
Reg
10
11
12
13
VDD
OUT2A
MS2
MS1
SENSE2 14
VBB2
AGND and PGND must be
connected together externally
26184.23D