A3950

更新时间： 2024-02-27 13:21:40

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动器
页数	文件大小	规格书
9页	318K
描述
DMOS Full-Bridge Motor Driver

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技术参数
数据手册

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A3950 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	HTSSOP, TSSOP16,.25
针数：	16	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	7.9	Samacsys Confidence：	4
Samacsys Status：	Released	2D Presentation：	https://componentsearchengine.com/2D/0T/520598.1.1.png
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=520598	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=520598
3D View：	https://componentsearchengine.com/viewer/3D.php?partID=520598	Samacsys PartID：	520598
Samacsys Image：	https://componentsearchengine.com/Images/9/A3950SLP-T.jpg	Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/A3950SLP-T.jpg
Samacsys Pin Count：	17	Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages	Samacsys Footprint Name：	16 TSSOP+EP
Samacsys Released Date：	2017-12-17 22:52:25	Is Samacsys：	N
模拟集成电路 - 其他类型：	BRUSH DC MOTOR CONTROLLER	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	2	功能数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-20 °C	最大输出电流：	2.8 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	HTSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	8/36 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Motion Control Electronics
最大供电电流 (Isup)：	8.5 mA	最大供电电压 (Vsup)：	36 V
最小供电电压 (Vsup)：	8 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	4.4 mm	Base Number Matches：	1

A3950 数据手册

Preliminary Data Sheet

Subject to Change without Notice

November 4, 2005

A3950

DMOS Full-Bridge Motor Driver

Functional Description

applying an enable chop command. Because it is possible to

drive current in both directions through the DMOS switches,

this configuration effectively shorts out the motor generated

BEMF as long as the ENABLE chop mode is asserted. The

maximum current can be approximated by V_BEMF/R_L. Care

should be taken to insure that the maximum ratings of the

device are not exceeded in worse case braking situations:

high speed and high-inertia loads.

VREG. This supply voltage is used to run the sink-side

DMOS outputs. VREG is internally monitored and in the

case of a fault condition, the outputs of the device are dis-

abled. The VREG pin should be decoupled with a 0.22 μF

capacitor to ground.

Charge Pump. The charge pump is used to generate a

supply above V_BBto drive the source-side DMOS gates. A

0.1 μF ceramic monolithic capacitor should be connected

between CP1 and CP2 for pumping purposes. A 0.1 μF

ceramic monolithic capacitor should be connected between

VCP and VBB to act as a reservoir to run the high-side

DMOS devices. The VCP voltage level is internally moni-

tored and, in the case of a fault condition, the outputs of the

device are disabled.

Overcurrent Protection. The voltage on the output pins

relative to supply are monitored to ensure that the motor lead

is not shorted to supply or ground. If a short is detected, the

full-bridge outputs are turned off, flag NFAULT is driven

low, and a 1.2 ms fault timer is started.

After this 1.2 ms period, t_OCP, the device will then be

allowed to follow the input commands and another turn-on is

attempted. If there is still a fault condition, the cycle repeats.

If, after t_OCPexpires, it is determined that the short condi-

tion is not present, the NFAULT pin is released and normal

operation resumes.

Shutdown. In the event of a fault due to excessive junction

temperature, or low voltage on VCP or VREG, the outputs of

the device are disabled until the fault condition is removed.

At power-on the UVLO circuit disables the drivers.

Sleep Mode. Control input SLEEP is used to minimize

power consumption when the A3950 not in use. This disables

much of the internal circuitry, including the regulator and

charge pump. A logic low setting puts the device into Sleep

mode, and a logic high setting allows normal operation. After

coming out of Sleep mode, provide a 1 ms interval before

applying PWM signals, to to allow the charge pump to

stabilize.

Diagnostic Output. The NFAULT pin signals a problem

with the chip via an open drain output. A motor fault, under-

voltage condition, or T_J> 160°C will drive the pin active

low. This output is not valid when SLEEP puts the device

into minimum power dissipation mode.

TSD. Two die temperature monitors are integrated on the

chip. As die temperature increases towards the maximum, a

thermal warning signal will be triggered at 160°C. This fault

drives the NFAULT low, but does not disable the operation of

the chip. If the die temperature increases further, to approxi-

mately 175°C, the full-bridge outputs will be disabled until

the internal temperature falls below a hysteresis of 15°C.

MODE. Control input MODE is used to toggle between

fast decay mode and slow decay mode. A logic high puts

the device in slow decay mode. Synchronus rectification is

always enabled.

Braking. The braking function is implemented by driving

the device in slow decay mode via the MODE setting and

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

A3950DS

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

1...3 4 567 8 9

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