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A32300DX-1PQG240C PDF预览

A32300DX-1PQG240C

更新时间: 2022-12-01 21:20:46
品牌 Logo 应用领域
ACTEL
页数 文件大小 规格书
22页 217K
描述
Field Programmable Gate Array, 1888 CLBs, 30000 Gates, CMOS, PQFP240, PLASTIC, QFP-240

A32300DX-1PQG240C 数据手册

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Lo g ic Mo d u le s  
The 3200DX contains three types of logic modules:  
combinatorial (C-modules), sequential (S-modules), and  
decode (D-modules). Both the C-module and S-module are  
identical to the 1200XL family logic modules.  
A0  
B0  
S0  
D00  
D00  
D10  
D11  
The combinatorial module (shown in Figure 1) implements  
the following function:  
Y
Y=!S1*!S0*D00+!S1*S0*D01*S1*!S0*D01+S1*S0*D11  
where:  
S0=A0*B0  
S1=A1 + B1  
S1  
The S-module is designed to implement high-speed flip-flop  
functions within a single module. The S-module implements  
the same logic function as the C-module followed by a  
sequential block. The sequential block can implement either a  
D flip-flop or a transparent latch. The S-module can also be  
configured as fully transparent so that it can be used to  
implement purely combinatorial logic. The function of the  
sequential module is determined by the macro selection from  
the design library. The available S-module implementations  
A1  
B1  
Figure 1 C-module Implementation  
are shown in Figure 2.  
D-modules are arranged around the periphery of the device  
and contain wide decode circuits providing a fast decode  
function similar to CPLDs and PALs (Figure 3). This is  
D00  
D01  
D00  
D01  
OUT  
OUT  
Y
D
Q
Y
D
Q
D10  
D10  
S0  
D11  
S1  
D11  
S1  
S0  
GATE  
CLR  
Up to 7-input function plus D-type flip-flop with clear  
Up to 7-input function plus latch  
D00  
D01  
D0  
Y
OUT  
OUT  
Y
D
Q
D10  
S0  
D1  
D11  
S1  
GATE  
S
CLR  
Up to 8-input function (same as C-module)  
Up to 4-input function plus latch with clear  
Figure 2 S-module Implementations  
4
 
 

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