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A29L160SERIES PDF预览

A29L160SERIES

更新时间: 2022-01-19 18:57:00
品牌 Logo 应用领域
其他 - ETC 闪存
页数 文件大小 规格书
45页 433K
描述
2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only. Boot Sector Flash Memory

A29L160SERIES 数据手册

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A29L160 Series  
Device erasure occurs by executing the proper erase  
command sequence. This initiates the Embedded Erase  
General Description  
The A29L160 is a 16Mbit, 3.0 volt-only Flash memory  
organized as 2,097,152 bytes of 8 bits or 1,048,576 words of  
16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16  
bits of data appear on I/O0~I/O15. The A29L160 is offered in  
48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This  
device is designed to be programmed in-system with the  
standard system 3.0 volt VCC supply. Additional 12.0 volt  
VPP is not required for in-system write or erase operations.  
However, the A29L160 can also be programmed in standard  
EPROM programmers.  
The A29L160 has the first toggle bit, I/O6, which indicates  
whether an Embedded Program or Erase is in progress, or it  
is in the Erase Suspend. Besides the I/O6 toggle bit, the  
A29L160 has a second toggle bit, I/O2, to indicate whether  
the addressed sector is being selected for erase. The  
A29L160 also offers the ability to program in the Erase  
Suspend mode. The standard A29L160 offers access times  
of 70, 90 and 120ns, allowing high-speed microprocessors to  
operate without wait states. To eliminate bus contention the  
algorithm  
-
an internal algorithm that automatically  
preprograms the array (if it is not already programmed)  
before executing the erase operation. During erase, the  
device automatically times the erase pulse widths and  
verifies proper erase margin. The Unlock Bypass mode  
facilitates faster programming times by requiring only two  
write cycles to program data instead of four.  
The host system can detect whether a program or erase  
operation is complete by observing the RY /  
pin, or by  
BY  
reading the I/O7 (  
Polling) and I/O6 (toggle) status bits.  
Data  
After a program or erase cycle has been completed, the  
device is ready to read array data or accept another  
command.  
The sector erase architecture allows memory sectors to be  
erased and reprogrammed without affecting the data  
contents of other sectors. The A29L160 is fully erased when  
shipped from the factory.  
The hardware sector protection feature disables operations  
for both program and erase in any combination of the  
sectors of memory. This can be achieved via programming  
equipment.  
The Erase Suspend/Erase Resume feature enables the user  
to put erase on hold for any period of time to read data from,  
or program data to, any other sector that is not selected for  
erasure. True background erase can thus be achieved.  
device has separate chip enable (  
), write enable (  
)
WE  
CE  
and output enable (  
) controls.  
OE  
The device requires only a single 3.0 volt power supply for  
both read and write functions. Internally generated and  
regulated voltages are provided for the program and erase  
operations.  
The A29L160 is entirely software command set compatible  
with the JEDEC single-power-supply Flash standard.  
Commands are written to the command register using  
standard microprocessor write timings. Register contents  
serve as input to an internal state-machine that controls the  
erase and programming circuitry. Write cycles also internally  
latch addresses and data needed for the programming and  
erase operations. Reading data out of the device is similar to  
reading from other Flash or EPROM devices.  
Device programming occurs by writing the proper program  
command sequence. This initiates the Embedded Program  
algorithm - an internal algorithm that automatically times the  
program pulse widths and verifies proper program margin.  
The hardware  
pin terminates any operation in  
RESET  
progress and resets the internal state machine to reading  
array data. The pin may be tied to the system reset  
RESET  
circuitry. A system reset would thus also reset the device,  
enabling the system microprocessor to read the boot-up  
firmware from the Flash memory.  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of time,  
the device enters the automatic sleep mode. The system can  
also place the device into the standby mode. Power  
consumption is greatly reduced in both these modes.  
PRELIMINARY  
(July, 2002, Version 0.0)  
2
AMIC Technology, Inc.  

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