A29DL32x Series
Accelerated Program Operation
Word/Byte Configuration
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
The
pin determines whether the I/O pins I/O15-I/O0
BYTE
operate in the byte or word configuration. If the
pin is
BYTE
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by and
the
/ACC pin. This function is primarily intended to allow
WP
faster manufacturing throughput at the factory.
.
OE
CE
If the system asserts VHH on this pin, the device automatically
enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
If the
pin is set at logic “0”, the device is in byte
BYTE
configuration, and only I/O0-I/O7 are active and controlled by
and . I/O8-I/O14 are tri-stated, and I/O15 pin is used
CE
OE
as an input for the LSB(A-1) address function.
mode. Removing VHH from the
/ACC pin returns the
WP
Requirements for Reading Array Data
device to normal operation. Note that the
not be at VHH for operations other than accelerated program-
ming, or device damage may result. In addition, the
/ACC pin must
WP
To read array data from the outputs, the system must drive
the
and
pins to VIL.
is the power control and
CE
OE
CE
/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
WP
selects the device.
OE
data to the output pins.
is the output control and gates array
should remain at VIH. The
WE
Autoselect Functions
pin determines whether the device outputs array data
in words or bytes.
BYTE
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7-I/O0. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
Simultaneous Read/Write Operations with Zero
Latency
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, lCC1 in the DC Characteristics table represents the
active current specification for reading array data.
This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to read
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. ICC6 and ICC7 in the DC Characteristics
table represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
and
to VIL, and
CE
WE
Standby Mode
to VIH.
OE
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
For program operations, the
the device accepts program data in bytes or words, Refer to
“Word/Byte Configuration” for more information.
pin determines whether
BYTE
placed in the high impedance state, independent of the
input.
OE
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The “Word / Byte Program Command
Sequence” section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables 3-4 indicate the
address range that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the larger, code
sectors of uniform size. A “bank address” is the address bits
required to uniquely select a bank. Similarly, a “sector
address” is the address bits required to uniquely select a
sector.
The device enters the CMOS standby mode when the
&
CE
pins are both held at VCC ± 0.3V. (Note that this is a
RESET
more restricted voltage range than VIH.) If
and
CE
RESET
are held at VIH, but not within VCC ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) for read
access when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represent the standby
current specification.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
PRELIMINARY (May, 2005, Version 0.0)
6
AMIC Technology, Corp.
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