A29DL32x Series
The
pin may be tied to the system reset circuitry. A
RESET
Automatic Sleep Mode
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
If
is asserted during a program or erase operation,
RESET
sleep mode is independent of the
,
and
control
OE
WE
CE
the RY/
pin remains a “0” (busy) until the internal reset
BY
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep
mode current specification.
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
RY/
BY
complete. If
to determine whether the reset operation is
is asserted when a program or erase
RESET
operation is not executing (RY/
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
pin is “1”), the reset
BY
: Hardware Reset Pin
RESET
The
pin provides a hardware method of resetting
RESET
the device to reading array data. When the system drives the
pin low for at least a period of tRP, the device
the
pin return to VIH.
RESET
Refer to the AC Characteristics tables for
parameters and diagram.
RESET
RESET
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
Output Disable Mode
the duration of the
pulse. The device also resets the
RESET
When the
input is at VIH, output from the device is
OE
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
disabled. The output pins are placed in the high impedance
state.
Current is reduced for the duration of the
pulse.
RESET
When
is held at VSS ± 0.3V, the device draws
RESET
CMOS standby current (ICC4 ). If
is held at VIL but not
RESET
within VSS ± 0.3V, the standby current will be greater.
Table 2. A29DL32x Device Bank Divisions
Device
Part Number
Bank 1
Sector Sizes
Bank 2
Sector Sizes
Megabits
Megabits
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Fifty-six
64 Kbyte/32 Kword
A29DL322
4 Mbit
28 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
A29DL323
A29DL324
8 Mbit
24 Mbit
16 Mbit
Eight 8 Kbyte/4 Kword,
Thirty one 64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
16 Mbit
(November, 2007, Version 1.2)
7
AMIC Technology, Corp.
5秒后页面跳转
电子元器件中的网络滤波器、EMI滤波器与EMC滤波器：分类关系与功能详解
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
