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A29512AV-90

更新时间： 2024-01-14 04:19:19

品牌	Logo	应用领域
联笙电子 - AMICC		内存集成电路光电二极管
页数	文件大小	规格书
31页	295K
描述
64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory

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A29512AV-90 技术参数

是否Rohs认证：	不符合	生命周期：	Contact Manufacturer
包装说明：	TSOP1, TSSOP32,.8,20	Reach Compliance Code：	unknown
风险等级：	5.88	最长访问时间：	90 ns
命令用户界面：	YES	数据轮询：	YES
JESD-30 代码：	R-PDSO-G32	长度：	18.4 mm
内存密度：	524288 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
部门数/规模：	2	端子数量：	32
字数：	65536 words	字数代码：	64000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	64KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP1
封装等效代码：	TSSOP32,.8,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	并行/串行：	PARALLEL
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	部门规模：	32K
最大待机电流：	0.000005 A	子类别：	Flash Memories
最大压摆率：	0.04 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
切换位：	YES	类型：	NOR TYPE
宽度：	8 mm	Base Number Matches：	1

A29512AV-90 数据手册

A29512A Series

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

ICC2 in the Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the

and

pins to VIL.

is the power control and

selects the device.

is the output control and gates

array data to the output pins.

should remain at VIH all

the time during read operation. The internal state machine

is set for reading array data upon device power-up, or after

a hardware reset. This ensures that no spurious alteration

of the memory content occurs during the power transition.

No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data

on the device data outputs. The device remains enabled for

read access until the command register contents are

altered.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O7 - I/O0. Standard read cycle timings and ICC read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section

for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to

the Read Operations Timings diagram for the timing

waveforms, lCC1 in the DC Characteristics table represents

the active current specification for reading array data.

placed in the high impedance state, independent of the

input.

The device enters the CMOS standby mode when the

Writing Commands/Command Sequences

is held at VCC ± 0.5V. (Note that this is a more restricted

voltage range than VIH.) The device enters the TTL standby

To write a command or command sequence (which

includes programming data to the device and erasing

mode when

is held at VIH. The device requires the

sectors of memory), the system must drive

and

standard access time (tCE) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

ICC3 in the DC Characteristics tables represents the standby

current specification.

VIL, and

to VIH. An erase operation can erase one

sector, multiple sectors, or the entire device. The Sector

Address Tables indicate the address range that each sector

occupies. A "sector address" consists of the address inputs

required to uniquely select a sector. See the "Command

Definitions" section for details on erasing a sector or the

entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can

then read autoselect codes from the internal register (which

is separate from the memory array) on I/O7 - I/O0. Standard

read cycle timings apply in this mode. Refer to the

Output Disable Mode

When the

input is at VIH, output from the device is

disabled. The output pins are placed in the high impedance

state.

PRELIMINARY

(August, 2002, Version 0.0)

AMIC Technology, Inc.

1...3 4 567 8 9...31

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型号	品牌	描述	获取价格	数据表
A29512L-55	AMICC	64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29512L-70	AMICC	64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29512L-90	AMICC	64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29512V-55	AMICC	64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29512V-70	AMICC	64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格
A29512V-90	AMICC	64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory	获取价格

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