A29040B Series
512K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Preliminary
Features
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
ꢀ5.0V ± 10% for read and write operations
ꢀAccess times:
ꢀTypical 100,000 program/erase cycles per sector
- 55/70/90 (max.)
ꢀCurrent:
ꢀ20-year data retention at 125°C
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
- Reliable operation for the life of the system
ꢀCompatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
ꢀFlexible sector architecture
- Superior inadvertent write protection
- 8 uniform sectors of 64 Kbyte each
- Any combination of sectors can be erased
- Supports full chip erase
ꢀ
Polling and toggle bits
Data
- Provides a software method of detecting completion of
program or erase operations
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within that
sector
ꢀErase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
ꢀExtended operating temperature range: -40°C~+85°C
for –U series
ꢀPackage options
ꢀEmbedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors
and verify the erased sectors
- 32-pin P-DIP, PLCC, or TSOP (Forward type)
General Description
Reading data out of the device is similar to reading from
other Flash or EPROM devices.
The A29040B is a 5.0 volt-only Flash memory organized as
524,288 bytes of 8 bits each. The 512 Kbytes of data are
further divided into eight sectors of 64 Kbytes each for flexible
sector erase capability. The 8 bits of data appear on I/O0 -
I/O7 while the addresses are input on A0 to A18. The
A29040B is offered in 32-pin PLCC, TSOP, and PDIP
packages. This device is designed to be programmed in-
system with the standard system 5.0volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write or
erase operations. However, the A29040B can also be
programmed in standard EPROM programmers.
The A29040B has a second toggle bit, I/O2, to indicate
whether the addressed sector is being selected for erase, and
also offers the ability to program in the Erase Suspend mode.
The standard A29040B offers access times of 55, 70 and 90
ns, allowing high-speed microprocessors to operate without
wait states. To eliminate bus contention the device has
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
-
an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 (
Polling) and
Data
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
separate chip enable (
), write enable (
) and output
WE
CE
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29040B is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors
of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
enable (
) controls.
OE
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29040B is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
PRELIMINARY (December, 2004, Version 0.2)
1
AMIC Technology, Corp.
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