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A29002U-150F PDF预览

A29002U-150F

更新时间: 2024-01-16 02:35:15
品牌 Logo 应用领域
联笙电子 - AMICC 光电二极管内存集成电路
页数 文件大小 规格书
35页 393K
描述
Flash, 256KX8, 150ns, PDIP32, LEAD FREE, PLASTIC, DIP-32

A29002U-150F 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
零件包装代码:DIP包装说明:LEAD FREE, PLASTIC, DIP-32
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.56最长访问时间:150 ns
其他特性:BOTTOM BOOT SECTOR启动块:BOTTOM
命令用户界面:YES数据轮询:YES
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PDIP-T32
长度:41.91 mm内存密度:2097152 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1部门数/规模:1,2,1,3
端子数量:32字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP32,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL电源:5 V
编程电压:5 V认证状态:Not Qualified
座面最大高度:5.334 mm部门规模:16K,8K,32K,64K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.04 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
切换位:YES类型:NOR TYPE
宽度:15.24 mmBase Number Matches:1

A29002U-150F 数据手册

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A29002/A290021 Series  
Standby Mode  
Requirements for Reading Array Data  
When the system is not reading or writing to the device, it  
can place the device in the standby mode. In this mode,  
current consumption is greatly reduced, and the outputs are  
To read array data from the outputs, the system must drive  
the  
and  
pins to VIL.  
is the power control and  
CE  
OE  
CE  
selects the device.  
OE  
data to the output pins.  
is the output control and gates array  
placed in the high impedance state, independent of the  
input.  
OE  
should remain at VIH all the time  
WE  
during read operation. The internal state machine is set for  
reading array data upon device power-up, or after a  
hardware reset. This ensures that no spurious alteration of  
the memory content occurs during the power transition. No  
command is necessary in this mode to obtain array data.  
Standard microprocessor read cycles that assert valid  
addresses on the device address inputs produce valid data  
on the device data outputs. The device remains enabled for  
read access until the command register contents are altered.  
See "Reading Array Data" for more information. Refer to the  
AC Read Operations table for timing specifications and to the  
Read Operations Timings diagram for the timing waveforms,  
lCC1 in the DC Characteristics table represents the active  
current specification for reading array data.  
The device enters the CMOS standby mode when the  
&
CE  
pins (  
only on A290021) are both held at VCC ±  
CE  
0.5V. (Note that this is a more restricted voltage range than  
VIH.) The device enters the TTL standby mode when is  
RESET  
CE  
(Not available on A290021) is held  
held at VIH, while  
RESET  
at VCC±0.5V. The device requires the standard access time  
(tCE) before it is ready to read data.  
If the device is deselected during erasure or programming,  
the device draws active current until the operation is  
completed.  
ICC3 in the DC Characteristics tables represents the standby  
current specification.  
Output Disable Mode  
Writing Commands/Command Sequences  
When the  
input is at VIH, output from the device is  
OE  
To write a command or command sequence (which includes  
programming data to the device and erasing sectors of  
disabled. The output pins are placed in the high impedance  
state.  
memory), the system must drive  
and  
to VIL, and  
CE  
WE  
to VIH. An erase operation can erase one sector,  
OE  
: Hardware Reset Pin (N/A on A290021)  
RESET  
multiple sectors, or the entire device. The Sector Address  
Tables indicate the address range that each sector occupies.  
A "sector address" consists of the address inputs required to  
uniquely select a sector. See the "Command Definitions"  
section for details on erasing a sector or the entire chip, or  
suspending/resuming the erase operation.  
The  
pin provides a hardware method of resetting  
RESET  
the device to reading array data. When the system drives the  
pin low for at least a period of tRP, the device  
RESET  
immediately terminates any operation in progress, tristates  
all data output pins, and ignores all read/write attempts for  
After the system writes the autoselect command sequence,  
the device enters the autoselect mode. The system can then  
read autoselect codes from the internal register (which is  
separate from the memory array) on I/O7 - I/O0. Standard  
read cycle timings apply in this mode. Refer to the  
"Autoselect Mode" and "Autoselect Command Sequence"  
sections for more information.  
ICC2 in the Characteristics table represents the active current  
specification for the write mode. The "AC Characteristics"  
section contains timing specification tables and timing  
diagrams for write operations.  
the duration of the  
pulse. The device also resets the  
RESET  
internal state machine to reading array data. The operation  
that was interrupted should be reinitiated once the device is  
ready to accept another command sequence, to ensure data  
integrity.  
The  
pin may be tied to the system reset circuitry. A  
RESET  
system reset would thus also reset the Flash memory,  
enabling the system to read the boot-up firmware from the  
Flash memory.  
Refer to the AC Characteristics tables for  
parameters and diagram.  
RESET  
Program and Erase Operation Status  
During an erase or program operation, the system may  
check the status of the operation by reading the status bits  
on I/O7 - I/O0. Standard read cycle timings and ICC read  
specifications apply. Refer to "Write Operation Status" for  
more information, and to each AC Characteristics section for  
timing diagrams.  
(December, 2010, Version 1.6)  
5
AMIC Technology, Corp.  

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