A25LQ080 Series
PIN DESCRIPTION
Chip Select (
)
Write Protect (
)
W
S
The Write Protect ( ) pin can be used to prevent the Status
W
The SPI Chip Select ( ) pin enables and disables device
S
Register from being written. Used in conjunction with the
Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1
and BP0) bits and Status Register Protect (SRP0) bit, a
portion or the entire memory array can be hardware
operation. When Chip Select ( ) is high the device is
S
deselected and the Serial Data Output (DO, or IO0, IO1, IO2,
IO3) pins are at high impedance. When deselected, the
devices power consumption will be at standby levels unless
an internal erase, program or write status register cycle is in
progress.
protected. The Write Protect ( ) pin is active low.
W
When the QE bit of Status Register-2 is set for Quad I/O, the
Write Protect ( ) pin (Hardware Write Protect) function is
W
not available since this pin is used for IO2. See the Pin
Configuration for Quad I/O operation.
When Chip Select ( ) is brought low the device will be
S
selected, power consumption will increase to active levels
and instructions can be written to and data read from the
device. After power-up, Chip Select ( ) must transition from
S
high to low before a new instruction will be accepted.
Hold (
)
HOLD
The Hold (
) pin allows the device to be paused while
HOLD
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2,
IO3)
it is actively selected. When Hold (
) pin is brought low,
HOLD
while Chip Select ( ) pin is low, the DO pin will be at high
S
impedance and signals on the DI and Serial Clock (C) pins
The A25LQ080 support standard SPI, Dual SPI and Quad
SPI operation. Standard SPI instructions use the
unidirectional DI (input) pin to serially write instructions,
addresses or data to the device on the rising edge of the
Serial Clock (C) input pin. Standard SPI also uses the
unidirectional DO (output) to read data or status from the
device on the falling edge of Serial Clock (C).
Dual and Quad SPI instruction use the bidirectional IO pins
to serially write instructions, addresses or data to the device
on the rising edge of Serial clock (C) and read data or status
from the device on the falling edge of Serial Clock (C).
Quad SPI instructions require the non-volatile Quad Enable
bit (QE) in Status Register-2 to be set. When QE=1 the Write
will be ignored (don’t care). When Hold (
brought high, device operation can resume. The Hold
function can be useful when multiple devices are sharing the
) pin is
HOLD
same SPI signals. The Hold (
) pin is active low.
HOLD
When the QE bit of Status Register-2 is set for Quad I/O. the
Hold ( ) pin function is not available since this pin is
HOLD
used for IO3. See the Pin Configuration for Quad I/O
operation.
Serial Clock (C)
Protect (
becomes IO3.
) pin becomes IO2 and Hold (
) pin
HOLD
W
The SPI Serial Clock Input (C) pin provides the timing for
serial input and output operations.
(April, 2016, Version 1.0)
3
AMIC Technology Corp.
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