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A25L16P PDF预览

A25L16P

更新时间: 2024-02-19 18:33:41
品牌 Logo 应用领域
联笙电子 - AMICC 闪存
页数 文件大小 规格书
38页 511K
描述
16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface

A25L16P 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.8
Base Number Matches:1

A25L16P 数据手册

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A25L16P Series  
SIGNAL DESCRIPTION  
Serial Data Output (DO). This output signal is used to  
transfer data serially out of the device. Data is shifted out on  
the falling edge of Serial Clock (C).  
The DO pin is also used as an input pin when the Fast Read  
Dual Input-Output Function is executed.  
Serial Data Input / Output (DIO). This input signal is used to  
transfer data serially into the device. It receives instructions,  
addresses, and the data to be programmed. Values are  
latched on the rising edge of Serial Clock (C).  
The DIO pin is also used as an output pin when the Fast  
Read Dual Output function and Fast Read Dual Input-Output  
function are executed.  
Serial Clock (C). This input signal provides the timing of the  
serial interface. Instructions, addresses, or data present at  
Serial Data Input (DIO) are latched on the rising edge of  
Serial Clock (C). Data on Serial Data Output (DO) changes  
after the falling edge of Serial Clock (C).  
Status Register cycle is in progress, the device will be in the  
Standby mode (this is not the Deep Power-down mode).  
Driving Chip Select ( ) Low enables the device, placing it in  
S
the active power mode.  
After Power-up, a falling edge on Chip Select ( ) is required  
S
prior to the start of any instruction.  
Hold (  
). The Hold (  
) signal is used to pause  
HOLD  
HOLD  
any serial communications with the device without  
deselecting the device.  
During the Hold condition, the Serial Data Output (DO) is  
high impedance, and Serial Data Input (DIO) and Serial  
Clock (C) are Don’t Care. To start the Hold condition, the  
device must be selected, with Chip Select ( ) driven Low.  
S
Write Protect ( ). The main purpose of this input signal is  
W
to freeze the size of the area of memory that is protected  
against program or erase instructions (as specified by the  
values in the BP2, BP1 and BP0 bits of the Status Register).  
Chip Select ( ). When this input signal is High, the device  
S
is deselected and Serial Data Output (DO) is at high  
impedance. Unless an internal Program, Erase or Write  
SPI MODES  
the falling edge of Serial Clock (C).  
These devices can be driven by a microcontroller with its SPI  
peripheral running in either of the two following modes:  
– CPOL=0, CPHA=0  
– CPOL=1, CPHA=1  
For these two modes, input data is latched in on the rising  
edge of Serial Clock (C), and output data is available from  
The difference between the two modes, as shown in Figure 2,  
is the clock polarity when the bus master is in Stand-by mode  
and not transferring data:  
– C remains at 0 for (CPOL=0, CPHA=0)  
– C remains at 1 for (CPOL=1, CPHA=1)  
PRELIMINARY (April, 2007, Version 0.6)  
3
AMIC Technology Corp.  

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