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A1425A-3PG133C PDF预览

A1425A-3PG133C

更新时间: 2024-02-27 01:48:17
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟可编程逻辑
页数 文件大小 规格书
90页 4491K
描述
Field Programmable Gate Array, 310 CLBs, 2500 Gates, 250MHz, CMOS, CPGA133, HERMETIC SEALED, CERAMIC, PGA-133

A1425A-3PG133C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:HERMETIC SEALED, CERAMIC, PGA-133Reach Compliance Code:compliant
风险等级:5.88最大时钟频率:250 MHz
CLB-Max的组合延迟:2 nsJESD-30 代码:S-CPGA-P133
长度:34.544 mm可配置逻辑块数量:310
等效关口数量:2500端子数量:133
最高工作温度:70 °C最低工作温度:
组织:310 CLBS, 2500 GATES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:HPGA封装形状:SQUARE
封装形式:GRID ARRAY, HEAT SINK/SLUG可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
座面最大高度:8.13 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
宽度:34.544 mmBase Number Matches:1

A1425A-3PG133C 数据手册

 浏览型号A1425A-3PG133C的Datasheet PDF文件第4页浏览型号A1425A-3PG133C的Datasheet PDF文件第5页浏览型号A1425A-3PG133C的Datasheet PDF文件第6页浏览型号A1425A-3PG133C的Datasheet PDF文件第8页浏览型号A1425A-3PG133C的Datasheet PDF文件第9页浏览型号A1425A-3PG133C的Datasheet PDF文件第10页 
1 – ACT 3 Family Overview  
General Description  
Microsemi’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity  
programmable logic device. ACT 3 FPGAs offer a high performance, PCI compliant programmable  
solution capable of 186 MHz on-chip performance and 9.0 nanosecond clock-to-output (–1 speed grade),  
with capacities spanning from 1,500 to 10,000 gate array equivalent gates.  
The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and  
sequential logic modules used in Microsemi’s 3200DX and 1200XL families. In addition, the ACT 3 I/O  
modules contain registers which deliver 9.0 nanosecond clock-to-out times (–1 speed grade). The  
devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting  
very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high  
fanout signals such as flip-flop resets and output.  
The ACT 3 family is supported by Microsemi’s Designer Series Development System which offers  
automatic placement and routing (with automatic or fixed pin assignments), static timing analysis, user  
programming, and debug and diagnostic probe capabilities.  
Accumulators (16-Bit)  
47 MHz  
Loadable Counters (16-Bit)  
82 MHz  
Prescaled Loadable Counters (16-Bit)  
Shift Registers  
186 MHz  
186 MHz  
Figure 1-1 • Predictable Performance (worst-case commercial, –1 speed grade)  
System Performance Model  
Chip #1 I/O Module  
Chip #2 I/O Module  
35 pF  
I/O CLK  
I/O CLK  
tCKHS  
tTRACE  
tINSU  
Revision 3  
1-1  

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