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A1415AA-1BG208B

更新时间： 2022-12-14 23:57:37

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
68页	480K
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Accelerator Series FPGAs - ACT 3Family

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A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A r c h i t e c t u r e

Logic Modules

This section of the data sheet is meant to familiarize the user

with the architecture of the ACT 3 family of FPGA devices. A

generic description of the family will be presented first,

followed by a detailed description of the logic blocks, the

routing structure, the antifuses, and the special function

circuits. The on-chip circuitry required to program the

devices is not covered.

ACT 3 logic modules are enhanced versions of the 1200XL

family logic modules. As in the 1200XL family, there are two

types of modules: C-modules and S-modules. The C-module is

functionally equivalent to the 1200XL C-module and

implements high fanin combinatorial macros, such as 5-input

AND, 5-input OR, and so on. It is available for use as the CM8

hard macro. The S-module is designed to implement

high-speed sequential functions within a single module.

S-modules consist of a full C-module driving a flip-flop, which

allows an additional level of logic to be implemented without

additional propagation delay. It is available for use as the

DFM8A/B and DLM8A/B hard macros. C-modules and

S-modules are arranged in pairs called module-pairs.

Module-pairs are arranged in alternating patterns and make

up the bulk of the array. This arrangement allows the

placement software to support two-module macros of four

types (CC, CS, SC, and SS). The C-module implements the

following function:

T o p o lo g y

The ACT 3 family architecture is composed of six key

elements: Logic modules, I/O modules, I/O Pad Drivers,

Routing Tracks, Clock Networks, and Programming and Test

Circuits. The basic structure is similar for all devices in the

family, differing only in the number of rows, columns, and

I/Os. The array itself consists of alternating rows of modules

and channels. The logic modules and channels are in the

center of the array; the I/O modules are located along the

array periphery. A simplified floor plan is depicted in

Figure 1.

Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0

* D11

where: S0 = A0 * B0 and S1 = A1 + B1

An Array with n rows and m columns

c–1 c+1

m m+1 m+2 m+3

Columns

Rows

n+1

Channels

n+2

IO IO IO IO IO IO

Top I/Os

IO IO IO CLKM

n+1

IO IO BIN S

IO IO

n–1

•

n–1

•

IO IO

IO IO BIN S

Left I/Os

Right I/Os

Bottom I/Os

BIO IO IO IO IO IO

IO IO IO IO IO IO

Figure 1 • Generalized Floor Plan of ACT 3 Device

1 -1 8 1

1...4 5 678 9 10...68

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型号	品牌	描述	获取价格	数据表
A1415AA-1BG208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A1415AA-1BG208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A1415AA-1BG208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A1415AA-1CQ208B	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A1415AA-1CQ208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A1415AA-1CQ208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格

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