5秒后页面跳转
A14100AA-1PL208B PDF预览

A14100AA-1PL208B

更新时间: 2022-12-17 00:16:47
品牌 Logo 应用领域
ACTEL /
页数 文件大小 规格书
68页 480K
描述
Accelerator Series FPGAs - ACT 3Family

A14100AA-1PL208B 数据手册

 浏览型号A14100AA-1PL208B的Datasheet PDF文件第1页浏览型号A14100AA-1PL208B的Datasheet PDF文件第3页浏览型号A14100AA-1PL208B的Datasheet PDF文件第4页浏览型号A14100AA-1PL208B的Datasheet PDF文件第5页浏览型号A14100AA-1PL208B的Datasheet PDF文件第6页浏览型号A14100AA-1PL208B的Datasheet PDF文件第7页 
D e s c r i p t i o n  
The ACT 3 family is supported by Actels Designer Series  
Development System which offers automatic placement and  
routing (with automatic or fixed pin assignments), static  
timing anlaysis, user programming, and debug and diagnostic  
probe capabilities. The Designer Series is supported on the  
following platforms: 486/Pentium class PCs, Sun®‚ and HP®‚  
workstations. The software provides CAE interfaces to  
Cadence, Mentor Graphics®, OrCADand Viewlogic®‚  
design environments. Additional platforms are supported  
through Actels Industry Alliance Program, including DATA  
I/O (ABEL FPGA) and MINC.  
Actels ACT 3 Accelerator Series of FPGAs offers the  
industry’s fastest high-capacity programmable logic device.  
ACT 3 FPGAs offer a high perfomance, PCI compliant  
programmable solution capable of 250 MHz on-chip  
performance and 7.5 nanosecond clock-to-output, with  
capacities spanning from 1,500 to 10,000 gate array  
equivalent gates. For further information regarding PCI  
compliance of ACT 3 devices, see “Accelerator Series  
FPGAsACT 3 PCI Compliant Family.”  
The ACT 3 family builds on the proven two-module  
architecture consisting of combinatorial and sequential logic  
modules used in Actels 3200DX and 1200XL families. In  
addition, the ACT 3 I/O modules contain registers which  
deliver 7.5 nanosecond clock-to-out times. The devices  
contain four clock distribution networks, including dedicated  
array and I/O clocks, supporting very fast synchronous and  
asynchronous designs. In addition, routed clocks can be used  
to drive high fanout signals such as flip-flop resets and output  
enables.  
Predictable Performance* (Worst-Case Commercial)  
Accumulators (16-bit)  
63 MHz  
Loadable Counters (16-bit)  
110 MHz  
Prescaled Loadable Counters (16-bit)  
Shift Registers  
250 MHz  
250 MHz  
S y s t e m P e r f o r m a n c e M o d e l  
Chip #1  
Chip #2  
I/O Module  
I/O Module  
35 pF  
I/O CLK  
I/O CLK  
t
t
t
INSU  
CKHS  
TRACE  
Chip-to-Chip Performance  
(Worst-Case Commercial)  
t
t
t
Total  
MHz  
97  
CKHS  
TRACE  
INSU  
A1425A-3  
A1460A-3  
7.5  
1.0  
1.8  
10.3 ns  
11.3 ns  
9.0  
1.0  
1.3  
88  
1 -1 7 6  

与A14100AA-1PL208B相关器件

型号 品牌 描述 获取价格 数据表
A14100AA-1PL208C ACTEL Accelerator Series FPGAs - ACT 3Family

获取价格

A14100AA-1PL208I ACTEL Accelerator Series FPGAs - ACT 3Family

获取价格

A14100AA-1PL208M ACTEL Accelerator Series FPGAs - ACT 3Family

获取价格

A14100AA-1PQ208B ACTEL Accelerator Series FPGAs - ACT 3Family

获取价格

A14100AA-1PQ208C ACTEL Accelerator Series FPGAs - ACT 3Family

获取价格

A14100AA-1PQ208I ACTEL Accelerator Series FPGAs - ACT 3Family

获取价格