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A14100A-1RQG208I PDF预览

A14100A-1RQG208I

更新时间: 2024-02-11 17:26:06
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟现场可编程门阵列可编程逻辑
页数 文件大小 规格书
90页 4491K
描述
FPGA, 1377 CLBS, 10000 GATES, 125MHz, PQFP208, ROHS COMPLIANT, PLASTIC, RQFP-208

A14100A-1RQG208I 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:PLASTIC, BGA-313Reach Compliance Code:compliant
风险等级:5.83其他特性:MAX 228 I/OS
最大时钟频率:100 MHzCLB-Max的组合延迟:3 ns
JESD-30 代码:S-PBGA-B313JESD-609代码:e1
长度:35 mm湿度敏感等级:3
可配置逻辑块数量:1377等效关口数量:10000
端子数量:313最高工作温度:70 °C
最低工作温度:组织:1377 CLBS, 10000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:IBGA
封装形状:SQUARE封装形式:GRID ARRAY, INTERSTITIAL PITCH
峰值回流温度(摄氏度):245可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:2.52 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:2.54 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:35 mm
Base Number Matches:1

A14100A-1RQG208I 数据手册

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1 – ACT 3 Family Overview  
General Description  
Microsemi’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity  
programmable logic device. ACT 3 FPGAs offer a high performance, PCI compliant programmable  
solution capable of 186 MHz on-chip performance and 9.0 nanosecond clock-to-output (–1 speed grade),  
with capacities spanning from 1,500 to 10,000 gate array equivalent gates.  
The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and  
sequential logic modules used in Microsemi’s 3200DX and 1200XL families. In addition, the ACT 3 I/O  
modules contain registers which deliver 9.0 nanosecond clock-to-out times (–1 speed grade). The  
devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting  
very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high  
fanout signals such as flip-flop resets and output.  
The ACT 3 family is supported by Microsemi’s Designer Series Development System which offers  
automatic placement and routing (with automatic or fixed pin assignments), static timing analysis, user  
programming, and debug and diagnostic probe capabilities.  
Accumulators (16-Bit)  
47 MHz  
Loadable Counters (16-Bit)  
82 MHz  
Prescaled Loadable Counters (16-Bit)  
Shift Registers  
186 MHz  
186 MHz  
Figure 1-1 • Predictable Performance (worst-case commercial, –1 speed grade)  
System Performance Model  
Chip #1 I/O Module  
Chip #2 I/O Module  
35 pF  
I/O CLK  
I/O CLK  
tCKHS  
tTRACE  
tINSU  
Revision 3  
1-1  

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