Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
A1359
voltage increase is proportional to the magnitude of the magnetic
field applied. Conversely, the application of a north polarity field
decreases the output voltage from its quiescent value. For the
case of the reverse polarity device (A1359LLETR-RP-T), the
presence of a south-polarity magnetic field perpendicular to the
branded surface of the package face decreases the output volt-
age from its quiescent value toward the ground rail. The amount
of the output voltage decrease is proportional to the magnitude
of the magnetic field applied. Conversely, the application of a
north polarity field increases the output voltage from its quiescent
value. This proportionality is specified as the magnetic sensitiv-
ity, Sens (mV/G), of the device and is defined as:
Delay to Clamp A large magnetic input step may cause the
clamp to overshoot its steady state value. The delay to clamp,
tCLPVOUT, is defined as the time it takes for the output voltage
to settle within 1% of its steady state value after initially passing
through its steady state voltage. This is conceptually the same for
the PWM output duty cycle settling to the steady state value. (See
figure 4.)
Quiescent Voltage Output In the quiescent state (no signifi-
cant magnetic field: B = 0 G), the analog output, VOUT, is ratio-
metric to the supply voltage, VCC, throughout the entire operating
range of VCC. The PWM output, VPWMOUT, by virtue of being a
% duty-cycle will remain at 50% nominal throughout the entire
VCC operating range (4.5 to 5.5 V).
VOUT(BPOS) – VOUT(BNEG)
Sens
=
(2)
BPOS – BNEG
Quiescent Output Drift through Temperature Range Due
to internal component tolerances and thermal considerations, the
Quiescent Voltage Output, VOUT(Q) , may drift from its nominal
value across the operating ambient temperature, TA. For purposes
of specification, the Quiescent Voltage Output Drift Through
Temperature Range, ∆VOUT(Q) (mV), is defined as:
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Sensitivity Temperature Coefficient Device sensitivity
changes as temperature changes, with respect to its programmed
Sensitivity Temperature Coefficient, TCSENS. TCSENS is pro-
grammed at 150°C, and calculated relative to the nominal
sensitivity programming temperature of 25°C. TCSENS (%/°C) is
defined as:
VOUT(Q)(TA) – VOUT(Q)(25°C)
∆VOUT(Q)
=
(1)
Sensitivity Assuming the sensitivity of the device is positive
(Positive Polarity: A1359LLETR-T), the presence of a south-
polarity magnetic field perpendicular to the branded surface of
the package face increases the output voltage from its quiescent
value toward the supply voltage rail. The amount of the output
SensT2 – SensT1
1
(3)
100%
TCSENS
=
×
SensT1
T2–T1
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C. The
ideal value of Sens through the full ambient temperature range,
SensIDEAL(TA), is defined as:
Magnetic Input Signal
(4)
SensIDEAL(TA)
Sens × [100% +TCSENS (TA –T1)]
=
VCLP(HIGH)
T1
VPWMOUT or VOUT
tCLPPWM or
tCLPVOUT
Sensitivity Drift Due to Package Hysteresis Package
t1
t2
stress and relaxation can cause the device sensitivity at TA = 25°C
to change during and after temperature cycling. This change in
sensitivity follows a hysteresis curve. For purposes of specifica-
t1= time at which output voltage initially
reaches steady state clamp voltage
tion, the Sensitivity Drift Due to Package Hysteresis, ∆SensPKG
is defined as:
,
t2= time at which output voltage settles to
within 1% of steady state clamp voltage
Sens(25°C)2 – Sens(25°C)1
time (μs)
(5)
∆SensPKG
100 (%)
=
×
Sens(25°C)1
Figure 4. Definition of Delay to Clamp
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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