High Precision Linear Hall-Effect Sensor
With an Open Drain Pulse Width Modulated Output
A1356
OPERATING CHARACTERISTICS Valid over full operating temperature range, TA, VCC = 4.5 to 18 V, CBYPASS = 0.1 μF, unless
otherwise noted
Characteristics
Electrical Characteristics
Supply Voltage
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VCC
ICC
4.5
–
–
6
–
–
18
10
–
V
mA
V
Supply Current
Supply Zener Clamp Voltage
Power On Time1,2,3
VZsupply
tPO
ICC = 18 mA, TA = 25ºC, t < 5 min
fpwm = 2 kHz
28
–
4
ms
Small signal –3 dB, 100 G(P-P) magnetic input
signal
Internal Bandwidth
BWi
fC
–
–
400
200
–
–
Hz
Chopping Frequency4
TA = 25°C
kHz
Output Characteristics
IOUTSINK ≤ 20 mA, PWMOUT transistor on
–
–
–
–
0.6
0.5
80
V
V
PWMOUT Saturation Voltage
VSAT
IOUTSINK ≤ 10 mA, PWMOUT transistor on
PWMOUT Current Limit
ILIMIT
ILEAK
RL = 0 Ω
30
60
mA
VCC = 3.2 V, 0 V ≤ PWMOUT ≤ 24 V, PWMOUT
transistor off
PWMOUT Leakage Current
–
0.1
10
μA
PWMOUT Zener Clamp Voltage
PWMOUT Rise Time2,3
VZOUT
IOUTSINK = ILIMIT, TA = 25ºC
R = 2 kΩ, C = 20 pF
28
–
3
–
–
V
tr
tf
–
μs
μs
ms
ms
Ω
PWMOUT Fall Time2,3
R= 2 kΩ, C = 20 pF
–
–
3
–
Maximum Propagation Delay2,3
Response Time2,3
tpd(max)
1.5
–
tRESPONSE Impulse magnetic field of 300 G, fpwm = 2 kHz
–
–
2
Load Resistance (External)3
Load Capacitance (External)3
RL
CL
PWMOUT to VCC
PWMOUT to GND
2040
–
–
–
–
10
nF
Measured over 1000 output PWM clock periods,
3 sigma values, Sens = 60 m% / G
Duty Cycle Jitter2,3,5
JD
–
–
±0.090
% D
DCLP(HIGH)
DCLP(LOW)
90
5
–
–
95
10
% D
% D
Clamp Duty Cycle3
Pre-Programming Target6
Pre-Programming Quiescent Duty Cycle
Output
D(Q)PRE
B = 0 G, TA = 25°C
–
–
–
52
20
–
–
–
% D
(m% D)/G
kHz
Pre-Programming Sensitivity
SensPRE TA = 25°C
fPWMPRE TA = 25°C
Pre-Programming PWM Output Carrier
Frequency
2.8
Quiescent Duty Cycle Programming
Initial Quiescent Duty Cycle Output
D(Q)init
D(Q)
TA = 25°C
TA = 25°C
–
D(Q)PRE
–
–
% D
% D
Guaranteed Quiescent Duty Cycle
Output Range7
40
60
Quiescent Duty Cycle Output
Programming Bits
–
0.085
–
9
–
0.115
–
bit
Average Quiescent Duty Cycle Output
Step Size8,9
StepD(Q) TA = 25°C
ErrPGD(Q) TA = 25°C
0.100
% D
% D
Quiescent Duty Cycle Output
Programming Resolution10
StepD(Q)
× ±0. 5
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com