Datasheet > A1020B-PLG84M

A1020B-PLG84M

更新时间： 2022-12-01 19:50:05

品牌	Logo	应用领域
ACTEL		栅
页数	文件大小	规格书
24页	163K
描述
Field Programmable Gate Array, 547 CLBs, 2000 Gates, CMOS, PQCC84, PLASTIC, LCC-84

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A1020B-PLG84M 数据手册

™

A C T

1 S e r i e s F P G A s

A C T 1 A r r a y P e r f o r m a n c e

source 10 mA at TTL levels. See Electrical Specifications for

additional I/O buffer specifications.

T e m p e r a t u r e a n d Vo lt a g e E ffe c t s

Worst-case delays for ACT 1 arrays are calculated in the same

manner as for masked array products. A typical delay

parameter is multiplied by a derating factor to account for

temperature, voltage, and processing effects. However, in an

ACT 1 array, temperature and voltage effects are less

dramatic than with masked devices. The electrical

characteristics of module interconnections on ACT 1 devices

remain constant over voltage and temperature fluctuations.

D e v i c e O r g a n i z a t i o n

ACT 1 devices consist of a matrix of logic modules arranged in

rows separated by wiring channels. This array is surrounded

by a ring of peripheral circuits including I/O buffers,

testability circuits, and diagnostic probe circuits providing

real-time diagnostic capability. Between rows of logic

modules are routing channels containing sets of segmented

metal tracks with PLICE antifuses. Each channel has 22

signal tracks. Vertical routing is permitted via 13 vertical

tracks per logic module column. The resulting network allows

arbitrary and flexible interconnections between logic

modules and I/O modules.

As a result, the total derating factor from typical to

worst-case for a standard speed ACT 1 array is only 1.19 to 1,

compared to 2 to 1 for a masked gate array.

Lo g ic Mo d u le S iz e

Logic module size also affects performance. A mask

programmed gate array cell with four transistors usually

implements only one logic level. In the more complex logic

module (similar to the complexity of a gate array macro) of

an ACT 1 array, implementation of multiple logic levels

within a single module is possible. This eliminates interlevel

wiring and associated RC delays. The effect is termed “net

compression.”

P r o b e P i n

ACT 1 devices have two independent diagnostic probe pins.

These pins allow the user to observe any two internal signals

by entering the appropriate net name in the diagnostic

software. Signals may be viewed on a logic analyzer using

Actel’s Actionprobe^®diagnostic tools. The probe pins can

also be used as user-defined I/Os when debugging is finished.

O r d e r i n g I n f o r m a t i o n

A1010

–

Application (Temperature Range)

C = Commercial (0 to +70°C)

= Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PL = Plastic J-Leaded Chip Carriers

PQ = Plastic Quad Flatpacks

CQ = Ceramic Quad Flatpack

PG = Ceramic Pin Grid Array

VQ = Very Thin Quad Flatpack

Speed Grade

Blank = Standard Speed

–1

–2

–3

= Approximately 15% faster than Standard

= Approximately 25% faster than Standard

= Approximately 35% faster than Standard

Die Revision

B = 1.0 micron CMOS Process

Part Number

A1010 = 1200 Gates (5 V)

A1020 = 2000 Gates (5 V)

A10V10 = 1200 Gates (3.3 V)

A10V20 = 2000 Gates (3.3 V)

1 -2 8 5

1 234 5 6 7...24

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与A1020B-PLG84M相关器件

型号	品牌	描述	获取价格	数据表
A1020B-PQ100C	ETC	Field Programmable Gate Array (FPGA)	获取价格
A1020B-PQ100I	MICROSEMI	Field Programmable Gate Array, 547 CLBs, 2000 Gates, 40.5MHz, 547-Cell, CMOS, PQFP100, PLA	获取价格
A1020B-PQ100I	ACTEL	Field Programmable Gate Array, 547 CLBs, 2000 Gates, 40.5MHz, 547-Cell, CMOS, PQFP100, PLA	获取价格
A1020B-PQG100C	ACTEL	Field Programmable Gate Array, 547 CLBs, 2000 Gates, 45MHz, 547-Cell, CMOS, PQFP100, PLAST	获取价格
A1020B-PQG100I	ACTEL	Field Programmable Gate Array, 547 CLBs, 2000 Gates, 40.5MHz, 547-Cell, CMOS, PQFP100, PLA	获取价格
A1020BSB1	DBLECTRO	EDGE CARD IDC TYPE (REINFORCED TYPE)	获取价格

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