MC1455, MC1455B,
NCV1455B
Timers
The MC1455 monolithic timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation. Additional
terminals are provided for triggering or resetting if desired. In the time
delay mode, time is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free−running
frequency and the duty cycle are both accurately controlled with two
external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output structure can source or sink
up to 200 mA or drive MTTL circuits.
http://onsemi.com
MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
1455x
ALYW
G
Features
8
1
• Direct Replacement for NE555 Timers
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Current Output Can Source or Sink 200 mA
• Output Can Drive MTTL
• Temperature Stability of 0.005% per °C
• Normally ON or Normally OFF Output
• Pb−Free Packages are Available
1
8
1
PDIP−8
P1 SUFFIX
CASE 626
MC1455yyy
AWL
YYWWG
8
1
x
yyy
A
= B or V
= BP1 or P1
= Assembly Location
= Wafer Lot
L
Y, YY = Year
1.0 k
Load
MT2
W, WW = Work Week
G or G = Pb−Free Package
3
8
MT1
6
7
G
4
2
10 k
R
20ꢀM
C
MC1455
ORDERING INFORMATION
5
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
0.1 mF
0.01 mF
1.0 mF
1
1N4003
−10 V
3.5 k
250 V
−
10 mF
1N4740
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
V
CC
+
I
CC
V
R
Reset
4
8
700
Figure 1. 22 Second Solid State Time Delay Relay Circuit
7
5
V
CC
+
Control
Voltage
0.01 mF
Discharge
V
CC
MC1455
8
3
Threshold
6
V
S
5 k
2.0 k
Output
I
th
7
3
6
5
Discharge
Output
GND
1
Trigger
+
Threshold
I
V
O
Sink
Comp
A
2
Flip
Flop
I
Source
R
S
−
Control Voltage
Q
5 k
5 k
Inhibit/
Reset
+
Test circuit for measuring DC parameters (to set output and measure
parameters):
Comp
B
2
Trigger
−
a) When V w 2/3 V , V is low.
S
CC
O
b) When V v 1/3 V , V is high.
S
CC
O
c) When V is low, Pin 7 sinks current. To test for Reset, set V
O
O
1
4
c) high, apply Reset voltage, and test for current flowing into Pin 7.
c) When Reset is not in use, it should be tied to V
.
CC
GND
Reset
Figure 2. Representative Block Diagram
Figure 3. General Test Circuit
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
MC1455/D
February, 2006 − Rev. 9