SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14560B adds two 4–bit numbers in NBCD (natural binary coded
decimal) format, resulting in sum and carry outputs in NBCD code.
This device can also subtract when one set of inputs is complemented with
a 9’s Complementer (MC14561B).
All inputs and outputs are active high. The carry input for the least
P SUFFIX
PLASTIC
CASE 648
significant digit is connected to V
for no carry in.
SS
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
D SUFFIX
SOIC
CASE 751B
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
ORDERING INFORMATION
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
V
DD
– 0.5 to + 18.0
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
T
= – 55° to 125°C for all packages.
A
I , I
in out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
BLOCK DIAGRAM
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
7
C
S1
S2
S3
S4
13
12
11
10
9
in
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
A1
15
14
B1
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
A2
B2
A3
B3
A4
B4
1
2
3
4
5
6
TRUTH TABLE*
Input
Output
C
out
A4 A3 A2 A1 B4 B3 B2 B1
C
C
S4 S3 S2 S1
in
out
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
V
V
= PIN 16
= PIN 8
DD
SS
1
0
1
0
0
1
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
* Partial truth table to show logic operation for representative input values.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 30
1/94
Motorola, Inc. 19954
MOTOROLA CMOS LOGIC DATA
MC14560B
1